Browse Source
Initial support for SSD1322 OLED display driver. Only 1 bit color mode is supported. Most options map directly to values documented in the datasheet, except segments-per-pixel, which I had to add to support the Newhaven NHD-2.7-12864WDW3. This is a slightly odd feature, but in practice it is a lot nicer to support it in the driver, and since we're currently remapping pixels anyway, it makes sense to implement here. This driver also has a configurable buffer size for the pixel conversion. By using a larger buffer, we can potentially use DMA for the SPI transfer. The default is set to 8, which is the smallest value that supports segments-per-pixel = 2 Initial driver implementation by Lukasz Hawrylko <lukasz@hawrylko.pl>. Additional options and configurability by Tobias Pisani <mail@topisani.dev> Signed-off-by: Lukasz Hawrylko <lukasz@hawrylko.pl> Signed-off-by: Tobias Pisani <mail@topisani.dev> Co-authored-by: Lukasz Hawrylko <lukasz@hawrylko.pl> Co-authored-by: Tobias Pisani <mail@topisani.dev>pull/78936/head
Tobias Pisani
9 months ago
committed by
Henrik Brix Andersen
5 changed files with 459 additions and 0 deletions
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# Copyright (c) 2024 Lukasz Hawrylko |
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# SPDX-License-Identifier: Apache-2.0 |
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config SSD1322 |
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bool "SSD1322 display driver" |
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default y |
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depends on DT_HAS_SOLOMON_SSD1322_ENABLED |
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select MIPI_DBI |
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help |
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Enable driver for SSD1322 display driver. |
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/*
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* Copyright (c) 2024 Lukasz Hawrylko |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include "zephyr/sys/util.h" |
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#define DT_DRV_COMPAT solomon_ssd1322 |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(ssd1322, CONFIG_DISPLAY_LOG_LEVEL); |
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#include <string.h> |
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#include <zephyr/device.h> |
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#include <zephyr/init.h> |
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#include <zephyr/drivers/display.h> |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/drivers/mipi_dbi.h> |
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#include <zephyr/kernel.h> |
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#define SSD1322_SET_COLUMN_ADDR 0x15 |
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#define SSD1322_ENABLE_RAM_WRITE 0x5C |
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#define SSD1322_SET_ROW_ADDR 0x75 |
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#define SSD1322_SET_REMAP 0xA0 |
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#define SSD1322_SET_START_LINE 0xA1 |
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#define SSD1322_SET_DISPLAY_OFFSET 0xA2 |
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#define SSD1322_BLANKING_ON 0xA4 |
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#define SSD1322_BLANKING_OFF 0xA6 |
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#define SSD1322_EXIT_PARTIAL 0xA9 |
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#define SSD1322_DISPLAY_OFF 0xAE |
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#define SSD1322_DISPLAY_ON 0xAF |
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#define SSD1322_SET_PHASE_LENGTH 0xB1 |
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#define SSD1322_SET_CLOCK_DIV 0xB3 |
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#define SSD1322_SET_GPIO 0xB5 |
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#define SSD1322_SET_SECOND_PRECHARGE 0xB6 |
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#define SSD1322_DEFAULT_GREYSCALE 0xB9 |
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#define SSD1322_SET_PRECHARGE 0xBB |
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#define SSD1322_SET_VCOMH 0xBE |
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#define SSD1322_SET_CONTRAST 0xC1 |
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#define SSD1322_SET_MUX_RATIO 0xCA |
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#define SSD1322_COMMAND_LOCK 0xFD |
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struct ssd1322_config { |
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const struct device *mipi_dev; |
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struct mipi_dbi_config dbi_config; |
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uint16_t height; |
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uint16_t width; |
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uint16_t column_offset; |
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uint8_t row_offset; |
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uint8_t start_line; |
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uint8_t mux_ratio; |
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bool remap_row_first; |
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bool remap_columns; |
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bool remap_rows; |
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bool remap_nibble; |
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bool remap_com_odd_even_split; |
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bool remap_com_dual; |
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uint8_t segments_per_pixel; |
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uint8_t *conversion_buf; |
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uint16_t conversion_buf_size; |
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}; |
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static inline int ssd1322_write_command(const struct device *dev, uint8_t cmd, const uint8_t *buf, |
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size_t len) |
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{ |
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const struct ssd1322_config *config = dev->config; |
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return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, buf, len); |
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} |
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static int ssd1322_blanking_on(const struct device *dev) |
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{ |
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return ssd1322_write_command(dev, SSD1322_BLANKING_ON, NULL, 0); |
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} |
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static int ssd1322_blanking_off(const struct device *dev) |
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{ |
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return ssd1322_write_command(dev, SSD1322_BLANKING_OFF, NULL, 0); |
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} |
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/*
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* The controller uses 4-bit grayscale format, so one pixel is represented by 4 bits. |
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* Zephyr's display API does not support this format, so this uses mono01, and converts each 1-bit |
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* pixel to 1111 or 0000. |
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* |
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* buf_in: pointer to input buffer in mono01 format. This value will bel updated to point to |
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* the first byte after the last converted pixel. |
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* pixel_count: pointer to the total number of pixels in buf_in to convert. The number of |
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* converted pixels will be subtracted. |
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* returns the number of bytes written to buf_out. |
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*/ |
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static int ssd1322_conv_mono01_grayscale(const uint8_t **buf_in, uint32_t *pixel_count, |
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uint8_t *buf_out, size_t buf_out_size, |
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uint8_t segments_per_pixel) |
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{ |
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/* Output buffer size gets rounded down to avoid splitting chunks in the middle of input
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* bytes |
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*/ |
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uint16_t pixels_in_chunk = MIN(*pixel_count, ROUND_DOWN(buf_out_size / 2, 8)); |
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for (uint16_t in_idx = 0; in_idx < pixels_in_chunk; in_idx++) { |
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uint16_t seg_idx = in_idx * segments_per_pixel; |
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uint8_t color = ((*buf_in)[in_idx / 8] & BIT(in_idx % 8)) ? 0xF : 0; |
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buf_out[seg_idx / 2] = |
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(seg_idx % 2 == 0) ? color : ((color << 4) | buf_out[seg_idx / 2]); |
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} |
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buf_in += pixels_in_chunk / 8; |
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pixel_count -= pixels_in_chunk; |
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return pixels_in_chunk * segments_per_pixel / 2; |
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} |
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static int ssd1322_write_pixels(const struct device *dev, const uint8_t *buf, uint32_t pixel_count) |
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{ |
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const struct ssd1322_config *config = dev->config; |
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struct display_buffer_descriptor mipi_desc; |
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while (pixel_count > 0) { |
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size_t len; |
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int ret; |
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/* Other formats, such as RGB888 to grayscale could be added by switching here */ |
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len = ssd1322_conv_mono01_grayscale(&buf, &pixel_count, config->conversion_buf, |
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config->conversion_buf_size, |
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config->segments_per_pixel); |
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/* As the MIPI DBI interface also does not support 4bit grayscale, it is disguised
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* as a single row of mono01 pixels. While this could theoretically cause issues |
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* with some mipi-dbi implementations, the SPI-based driver ignores this metadata, |
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* and is likely the most relevant in practice. |
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*/ |
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mipi_desc.buf_size = len; |
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mipi_desc.width = len * 8; |
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mipi_desc.height = 1; |
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mipi_desc.pitch = mipi_desc.width; |
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ret = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config, |
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config->conversion_buf, &mipi_desc, |
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PIXEL_FORMAT_MONO01); |
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if (ret < 0) { |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static int ssd1322_write(const struct device *dev, const uint16_t x, const uint16_t y, |
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const struct display_buffer_descriptor *desc, const void *buf) |
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{ |
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const struct ssd1322_config *config = dev->config; |
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size_t buf_len; |
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int ret; |
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uint8_t cmd_data[2]; |
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int32_t pixel_count = desc->width * desc->height; |
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if (desc->pitch < desc->width) { |
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LOG_ERR("Pitch is smaller than width"); |
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return -EINVAL; |
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} |
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buf_len = MIN(desc->buf_size, desc->height * desc->width / 8); |
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if (buf == NULL || buf_len == 0U) { |
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LOG_ERR("Display buffer is not available"); |
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return -EINVAL; |
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} |
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if (desc->pitch > desc->width) { |
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LOG_ERR("Unsupported mode"); |
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return -EINVAL; |
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} |
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LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch, |
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desc->width, desc->height, buf_len); |
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cmd_data[0] = config->column_offset + (x >> 2) * config->segments_per_pixel; |
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cmd_data[1] = |
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config->column_offset + ((x + desc->width) >> 2) * config->segments_per_pixel - 1; |
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ret = ssd1322_write_command(dev, SSD1322_SET_COLUMN_ADDR, cmd_data, 2); |
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if (ret < 0) { |
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return ret; |
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} |
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cmd_data[0] = y; |
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cmd_data[1] = y + desc->height - 1; |
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ret = ssd1322_write_command(dev, SSD1322_SET_ROW_ADDR, cmd_data, 2); |
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if (ret < 0) { |
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return ret; |
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} |
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ret = ssd1322_write_command(dev, SSD1322_ENABLE_RAM_WRITE, NULL, 0); |
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if (ret < 0) { |
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return ret; |
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} |
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return ssd1322_write_pixels(dev, buf, pixel_count); |
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} |
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static int ssd1322_set_contrast(const struct device *dev, const uint8_t contrast) |
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{ |
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return ssd1322_write_command(dev, SSD1322_SET_CONTRAST, &contrast, 1); |
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} |
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static void ssd1322_get_capabilities(const struct device *dev, struct display_capabilities *caps) |
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{ |
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const struct ssd1322_config *config = dev->config; |
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memset(caps, 0, sizeof(struct display_capabilities)); |
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caps->x_resolution = config->width; |
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caps->y_resolution = config->height; |
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caps->supported_pixel_formats = PIXEL_FORMAT_MONO01; |
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caps->current_pixel_format = PIXEL_FORMAT_MONO01; |
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} |
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static int ssd1322_init_device(const struct device *dev) |
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{ |
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int ret; |
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uint8_t data[2]; |
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const struct ssd1322_config *config = dev->config; |
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ret = mipi_dbi_reset(config->mipi_dev, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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k_usleep(100); |
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ret = ssd1322_write_command(dev, SSD1322_DISPLAY_OFF, NULL, 0); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = 0x91; |
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ret = ssd1322_write_command(dev, SSD1322_SET_CLOCK_DIV, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = config->mux_ratio - 1; |
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ret = ssd1322_write_command(dev, SSD1322_SET_MUX_RATIO, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = config->start_line; |
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ret = ssd1322_write_command(dev, SSD1322_SET_START_LINE, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = config->row_offset; |
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ret = ssd1322_write_command(dev, SSD1322_SET_DISPLAY_OFFSET, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = 0x00; |
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data[1] = 0x01; |
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WRITE_BIT(data[0], 0, config->remap_row_first); |
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WRITE_BIT(data[0], 1, config->remap_columns); |
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WRITE_BIT(data[0], 2, config->remap_nibble); |
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WRITE_BIT(data[0], 4, config->remap_rows); |
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WRITE_BIT(data[0], 5, config->remap_com_odd_even_split); |
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WRITE_BIT(data[1], 4, config->remap_com_dual); |
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ret = ssd1322_write_command(dev, SSD1322_SET_REMAP, data, 2); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = 0x00; |
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ret = ssd1322_write_command(dev, SSD1322_SET_GPIO, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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ret = ssd1322_write_command(dev, SSD1322_DEFAULT_GREYSCALE, NULL, 0); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = 0xE2; |
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ret = ssd1322_write_command(dev, SSD1322_SET_PHASE_LENGTH, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = 0x1F; |
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ret = ssd1322_write_command(dev, SSD1322_SET_PRECHARGE, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = 0x08; |
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ret = ssd1322_write_command(dev, SSD1322_SET_SECOND_PRECHARGE, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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data[0] = 0x07; |
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ret = ssd1322_write_command(dev, SSD1322_SET_VCOMH, data, 1); |
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if (ret < 0) { |
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return ret; |
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} |
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ret = ssd1322_write_command(dev, SSD1322_EXIT_PARTIAL, NULL, 0); |
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if (ret < 0) { |
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return ret; |
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} |
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ret = ssd1322_blanking_on(dev); |
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if (ret < 0) { |
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return ret; |
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} |
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ret = ssd1322_write_command(dev, SSD1322_DISPLAY_ON, NULL, 0); |
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if (ret < 0) { |
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return ret; |
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} |
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return 0; |
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} |
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static int ssd1322_init(const struct device *dev) |
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{ |
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const struct ssd1322_config *config = dev->config; |
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if (!device_is_ready(config->mipi_dev)) { |
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LOG_ERR("MIPI not ready!"); |
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return -ENODEV; |
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} |
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int ret = ssd1322_init_device(dev); |
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if (ret < 0) { |
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LOG_ERR("Failed to initialize device, err = %d", ret); |
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return -EIO; |
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} |
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return 0; |
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} |
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static struct display_driver_api ssd1322_driver_api = { |
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.blanking_on = ssd1322_blanking_on, |
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.blanking_off = ssd1322_blanking_off, |
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.write = ssd1322_write, |
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.set_contrast = ssd1322_set_contrast, |
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.get_capabilities = ssd1322_get_capabilities, |
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}; |
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#define SSD1322_CONV_BUFFER_SIZE(node_id) \ |
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(DT_PROP(node_id, width) * DT_PROP(node_id, segments_per_pixel) * 4) |
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#define SSD1322_DEFINE(node_id) \ |
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static uint8_t conversion_buf##node_id[SSD1322_CONV_BUFFER_SIZE(node_id)]; \ |
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static const struct ssd1322_config config##node_id = { \ |
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.height = DT_PROP(node_id, height), \ |
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.width = DT_PROP(node_id, width), \ |
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.column_offset = DT_PROP(node_id, column_offset), \ |
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.row_offset = DT_PROP(node_id, row_offset), \ |
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.start_line = DT_PROP(node_id, start_line), \ |
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.mux_ratio = DT_PROP(node_id, mux_ratio), \ |
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.remap_row_first = DT_PROP(node_id, remap_row_first), \ |
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.remap_columns = DT_PROP(node_id, remap_columns), \ |
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.remap_rows = DT_PROP(node_id, remap_rows), \ |
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.remap_nibble = DT_PROP(node_id, remap_nibble), \ |
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.remap_com_odd_even_split = DT_PROP(node_id, remap_com_odd_even_split), \ |
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.remap_com_dual = DT_PROP(node_id, remap_com_dual), \ |
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.segments_per_pixel = DT_PROP(node_id, segments_per_pixel), \ |
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.mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ |
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.dbi_config = {.mode = MIPI_DBI_MODE_SPI_4WIRE, \ |
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.config = MIPI_DBI_SPI_CONFIG_DT( \ |
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node_id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8), 0)}, \ |
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.conversion_buf = conversion_buf##node_id, \ |
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.conversion_buf_size = sizeof(conversion_buf##node_id), \ |
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}; \ |
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\ |
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DEVICE_DT_DEFINE(node_id, ssd1322_init, NULL, NULL, &config##node_id, POST_KERNEL, \ |
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CONFIG_DISPLAY_INIT_PRIORITY, &ssd1322_driver_api); |
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|
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DT_FOREACH_STATUS_OKAY(solomon_ssd1322, SSD1322_DEFINE) |
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@ -0,0 +1,69 @@
@@ -0,0 +1,69 @@
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description: SSD1322 display controller |
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|
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compatible: "solomon,ssd1322" |
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|
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include: [mipi-dbi-spi-device.yaml, display-controller.yaml] |
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properties: |
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column-offset: |
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type: int |
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required: true |
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description: First visible column number. |
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row-offset: |
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type: int |
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default: 0 |
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description: | |
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COM pin used as first row, mapped to the line set by start-line. |
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The default corresponds to the reset value of the register. |
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start-line: |
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type: int |
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default: 0 |
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description: | |
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Starting line address of display ram (0-127). |
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The default corresponds to the reset value of the register. |
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mux-ratio: |
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type: int |
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default: 128 |
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description: | |
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COM Pin Multiplex ratio from 16-128. |
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The default corresponds to the reset value of the register. |
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remap-row-first: |
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type: boolean |
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description: Set scan direction to vertical first (swap rows/columns). |
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remap-columns: |
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type: boolean |
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description: Reverse the column order (flip horizontally). |
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|
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remap-rows: |
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type: boolean |
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description: Reverse the row order (flip vertically). |
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|
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remap-nibble: |
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type: boolean |
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description: Reverse every group of 4 nibbles. |
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remap-com-odd-even-split: |
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type: boolean |
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description: Odd even split of COM pins. |
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|
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remap-com-dual: |
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type: boolean |
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description: Dual COM mode. |
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segments-per-pixel: |
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type: int |
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default: 1 |
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enum: |
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- 1 |
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- 2 |
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description: | |
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Map multiple adjacent segments to one pixel. |
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Some displays (such as the Newhaven Display NHD-2.7-12864WDW3) connect |
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two adjacent pixel drivers to each physical pixel. By setting this to 2, |
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the driver will repeat each pixel. The default disables this functionality, |
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as it only applies to very specific display models. |
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