drivers: bbram: stm32-bbram: port to stm32wl

On STM32WL, the backup memory is defined as part of the TAMP peripheral.
This seems to be a deviation from the stm32 family where this memory is
defined as part of the RTC.

The STM32WL reference manual shows that tamp_pclk is connected to
rtc_pclk. This means that the clock required to run the TAMP peripheral
is the same as the RTC's. A quick port of BBRAM on STM32WL is achieved
by instanciating the bbram device as a child of the RTC and by modifying
the address offset to the first backup register from the rtc base
address.

Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>

drivers/bbram/bbram_stm32.c

@@ -14,7 +14,14 @@
 LOG_MODULE_REGISTER(bbram, CONFIG_BBRAM_LOG_LEVEL);
 
 #define STM32_BKP_REG_BYTES		 4
-#define STM32_BKP_REG_OFFSET		 0x50
+#ifdef TAMP
+/* If a SoC has a TAMP peripherals, then the backup registers are defined there,
+ * not in the RTC.
+ */
+#define STM32_BKP_REG_OFFSET		 (TAMP_BASE + offsetof(TAMP_TypeDef, BKP0R) - RTC_BASE)
+#else
+#define STM32_BKP_REG_OFFSET		 offsetof(RTC_TypeDef, BKP0R)
+#endif
 #define STM32_BKP_REG_INDEX(offset)	 ((offset) >> 2)
 #define STM32_BKP_REG_BYTE_INDEX(offset) ((offset)&0x3UL)
 #define STM32_BKP_REG(i)		 (((volatile uint32_t *)config->base_addr)[(i)])

dts/arm/st/wl/stm32wl.dtsi

@@ -207,6 +207,18 @@
 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
 			prescaler = <32768>;
 			status = "disabled";
+
+			/* In STM32WL, the backup registers are defined as part of the TAMP
+			 * peripheral. This peripheral is not implemented in Zephyr yet, however,
+			 * the reference manual states that tamp_pclk is connected to rtc_pclk.
+			 * It makes sense to have BBRAM instantiated as a child of RTC, so that
+			 * the driver can verify that its parent device (RTC) is ready.
+			 */
+			bbram: backup_regs {
+				compatible = "st,stm32-bbram";
+				st,backup-regs = <20>;
+				status = "disabled";
+			};
 		};
 
 		iwdg: watchdog@40003000 {