boards: raytac: Add support for raytac_an7002q_db

Add support for Raytac's new AN7002Q-DB.

Signed-off-by: Stanley Huang <stanley@raytac.com>

boards/raytac/an7002q_db/Kconfig

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+# Raytac AN7002Q-DB-5340 board configuration
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Raytac Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config IPM_NRFX
+	default IPM
+
+config MBOX_NRFX_IPC
+	default MBOX
+
+if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUAPP
+
+config BT_HCI_IPC
+	default y if BT
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BT_HCI_IPC
+
+endif
+
+if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUNET
+
+config BT_ECC
+	default y if BT
+
+endif

boards/raytac/an7002q_db/Kconfig.raytac_an7002q_db

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+# Copyright (c) 2024 Nordic Semiconductor
+# Copyright (c) 2025 Raytac Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RAYTAC_AN7002Q_DB
+	select SOC_NRF5340_CPUNET_QKAA if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUNET
+	select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUAPP

boards/raytac/an7002q_db/board.cmake

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Raytac Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUAPP)
+  board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
+elseif(CONFIG_BOARD_RAYTAC_AN7002Q_DB_NRF5340_CPUNET)
+  board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/raytac/an7002q_db/board.yml

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+board:
+  name: raytac_an7002q_db
+  full_name: AN7002Q-DB-5340
+  vendor: raytac
+  socs:
+    - name: nrf5340

boards/raytac/an7002q_db/doc/index.rst

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+.. zephyr:board:: raytac_an7002q_db
+
+Overview
+********
+
+The Raytac AN7002Q-DB-5340 is a single-board development kit for evaluation and development on
+the nRF7002, a Wi-Fi companion IC to Raytac's MDBT53 module host processor.
+It is certified for the Wi-Fi Alliance® `Wi-Fi Certification program`_ in the
+Connectivity, Security, and Optimization categories. See `UG Wi-Fi certification`_ for detailed
+information.
+
+The nRF7002 is an IEEE 802.11ax (Wi-Fi 6) compliant solution that implements the Wi-Fi physical
+layer and Medium Access Control (MAC) layer protocols. It implements the nRF Wi-Fi driver
+software on the nRF5340 host processor communicating over the QSPI bus.
+
+The nRF5340 host is a dual-core SoC based on the Arm® Cortex®-M33 architecture.
+It has the following features:
+
+* A full-featured Arm Cortex-M33F core with DSP instructions, FPU, and Armv8-M Security Extension,
+  running at up to 128 MHz, referred to as the application core.
+* A secondary Arm Cortex-M33 core, with a reduced feature set, running at a fixed 64 MHz,
+  referred to as the network core.
+
+The ``raytac_an7002q_db/nrf5340/cpuapp`` board target provides support for the application core on the
+nRF5340 SoC. The ``raytac_an7002q_db/nrf5340/cpunet`` board target provides support for the network
+core on the nRF5340 SoC.
+
+More information about the board can be found at the
+`Raytac AN7002Q-DB-5340 website`_.
+The `Raytac AN7002Q-DB-5340 Product Specification`_
+contains the processor's information and the datasheet.
+
+Hardware
+========
+
+* Raytac AN7002Q-DB-5340:
+  The Raytac AN7002Q-DB-5340 has two modules.
+
+  * The WiFi module of the AN7002Q-P.
+  * The BLE module of the MDBT5340-P.
+
+
+Supported features
+------------------
+
+.. zephyr:board-supported-hw::
+
+See `Raytac AN7002Q-DB-5340 Product Specification`_
+for a complete list of Raytac AN7002Q-DB-5340 board hardware features.
+
+Connections and IOs
+-------------------
+
+The connections and IOs supported by the development kit are listed in this section.
+
+LED
+^^^
+
+* **LED 1** (green) = **P1.06**
+* **LED 2** (green) = **P1.07**
+
+Push buttons
+^^^^^^^^^^^^
+
+* **Button 1** = **SW1** = **P1.08**
+* **Button 2** = **SW2** = **P1.09**
+
+Wi-Fi control
+^^^^^^^^^^^^^
+
+* BUCKEN = **P0.12**
+* HOST IRQ = **P0.23**
+* COEX_REQ = **P0.28**
+* COEX_STATUS0 = **P0.30**
+* COEX_STATUS1 = **P0.29**
+* COEX_GRANT = **P0.24**
+
+Security components
+-------------------
+
+The following security components are available:
+
+* Implementation Defined Attribution Unit (`IDAU`_) on the application core.
+
+  The IDAU is implemented with the System Protection Unit and is used to define
+  secure and non-secure memory maps. By default, the entire memory space
+  (Flash, SRAM, and peripheral address space) is defined to be secure-accessible only.
+
+* Secure boot.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The nRF5340 application core supports the Armv8-M Security Extension.
+Applications built for the ``raytac_an7002q_db/nrf5340/cpuapp`` board boot by default in the
+secure state.
+
+The nRF5340 network core does not support the Armv8-M Security Extension.
+nRF5340 IDAU can configure bus accesses by the nRF5340 network core to have the secure
+attribute set. This allows to build and run secure-only applications on the nRF5340 SoC.
+
+Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg|
+=============================================================================
+
+Applications on the nRF5340 may contain a Secure and a Non-Secure firmware
+image for the application core. The Secure image can be built using either
+Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware
+images are always built using Zephyr. The two alternatives are described below.
+
+.. note::
+
+   By default, SPE for the nRF5340 application core is built using TF-M.
+
+Building the Secure firmware with TF-M
+--------------------------------------
+
+The process to build the Secure firmware image using TF-M and the Non-Secure
+firmware image using Zephyr requires the following steps:
+
+1. Build the Non-Secure Zephyr application
+   for the application core using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp/ns``.
+   To invoke the building of TF-M the Zephyr build system requires the
+   Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by
+   default when building Zephyr as a Non-Secure application.
+   The Zephyr build system will perform the following steps automatically:
+
+   * Build the Non-Secure firmware image as a regular Zephyr application
+   * Build a TF-M (secure) firmware image
+   * Merge the output image binaries together
+   * Optionally build a bootloader image (MCUboot)
+
+.. note::
+
+   Depending on the TF-M configuration, an application DTS overlay may be
+   required, to adjust the Non-Secure image Flash and SRAM starting address
+   and sizes.
+
+2. Build the application firmware for the network core using
+   ``-DBOARD=raytac_an7002q_db/nrf5340/cpunet``.
+
+Building the Secure firmware using Zephyr
+-----------------------------------------
+
+The process to build the Secure and the Non-Secure firmware images
+using Zephyr requires the following steps:
+
+1. Build the Secure Zephyr application for the application core
+   using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp`` and
+   ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n``
+   in the application project configuration file.
+2. Build the Non-Secure Zephyr application for the application core
+   using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp/ns``.
+3. Merge the two binaries together.
+4. Build the application firmware for the network core using
+   ``-DBOARD=raytac_an7002q_db/nrf5340/cpunet``.
+
+When building a Secure/Non-Secure application for the nRF5340 application core,
+the Secure application will have to set the IDAU (SPU) configuration to allow
+Non-Secure access to all CPU resources utilized by the Non-Secure application
+firmware. SPU configuration shall take place before jumping to the Non-Secure
+application.
+
+Building a Secure only application
+==================================
+
+Build the Zephyr app in the usual way (see :ref:`build_an_application`
+and :ref:`application_run`), using ``-DBOARD=raytac_an7002q_db/nrf5340/cpuapp`` for
+the firmware running on the nRF5340 application core, and using
+``-DBOARD=raytac_an7002q_db/nrf5340/cpunet`` for the firmware running
+on the nRF5340 network core.
+
+Flashing
+========
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`. Then you can build and flash
+applications as usual (:ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. warning::
+
+   The nRF5340 has a flash read-back protection feature. When flash read-back
+   protection is active, you will need to recover the chip before reflashing.
+   If you are flashing with :ref:`west <west-build-flash-debug>`, run
+   this command for more details on the related ``--recover`` option:
+
+   .. code-block:: console
+
+      $ west flash -H -r nrfjprog --skip-rebuild
+
+.. note::
+
+   Flashing and debugging applications on the nRF5340 DK requires
+   upgrading the nRF Command Line Tools to version 10.12.0. Further
+   information on how to install the nRF Command Line Tools can be
+   found in :ref:`nordic_segger_flashing`.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application running on the
+nRF5340 application core.
+
+First, run your favorite terminal program to listen for output.
+
+.. code-block:: console
+
+   $ minicom -D <tty_device> -b 115200
+
+Replace :code:`<tty_device>` with the port where the board nRF7002 DK
+can be found. For example, under Linux, :code:`/dev/ttyACM0`.
+
+Then build and flash the application in the usual way.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: raytac_an7002q_db/nrf5340/cpuapp
+   :goals: build flash
+
+Debugging
+=========
+
+Refer to the :ref:`nordic_segger` page to learn about debugging Nordic
+boards with a Segger IC.
+
+Next steps
+**********
+
+You have now completed getting started with the Raytac AN7002Q-DB-5340.
+See the following links for where to go next:
+
+* `Installation`_ and `Configuring and Building`_ documentation to install the
+  nRF Connect SDK and learn more about its development environment.
+* `Developing with nRF70`_ documentation for more advanced topics related to the nRF70 Series.
+* `Wi-Fi`_ documentation for information related to Wi-Fi protocol and Wi-Fi modes of operation.
+
+References
+**********
+
+.. target-notes::
+
+.. _Wi-Fi Certification program:
+   https://www.wi-fi.org/certification
+.. _UG Wi-Fi certification:
+   https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/wifi_certification.html#ug-wifi-certification
+.. _IDAU:
+   https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
+.. _Raytac AN7002Q-DB-5340 website:
+   https://www.raytac.com/product/ins.php?index_id=139
+.. _Raytac AN7002Q-DB-5340 Product Specification:
+   https://www.raytac.com/download/index.php?index_id=79
+.. _Trusted Firmware M:
+   https://www.trustedfirmware.org/projects/tf-m/
+.. _Installation:
+   https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/installation.html#installation
+.. _Configuring and Building:
+   https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/config_and_build/index.html#configuration-and-build
+.. _Developing with nRF70:
+   https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf70/index.html#ug-nrf70-developing
+.. _Wi-Fi:
+   https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/protocols/wifi/index.html#ug-wifi

boards/raytac/an7002q_db/nrf5340_cpuapp_common.dtsi

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+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "nrf5340_cpuapp_common_pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-mcumgr = &uart0;
+		zephyr,bt-mon-uart = &uart0;
+		zephyr,bt-c2h-uart = &uart0;
+		zephyr,bt-hci = &bt_hci_ipc0;
+		nordic,802154-spinel-ipc = &ipc0;
+		zephyr,ieee802154 = &ieee802154;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	gpio_fwd: nrf-gpio-forwarder {
+		compatible = "nordic,nrf-gpio-forwarder";
+
+		status = "okay";
+
+		uart {
+			gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio1 5 0>, <&gpio1 4 0>;
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		pwm-led0 = &pwm_led0;
+		sw0 = &button0;
+		sw1 = &button1;
+		bootloader-led0 = &led0;
+		mcuboot-button0 = &button0;
+		mcuboot-led0 = &led0;
+		watchdog0 = &wdt0;
+	};
+
+	nrf_radio_coex: coex {
+		status = "okay";
+		compatible = "nordic,nrf7002-coex";
+		req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+		status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+		grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
+		swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&vregmain {
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&vregradio {
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&vregh {
+	status = "okay";
+};
+
+&adc {
+	status = "okay";
+};
+
+&gpiote {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c1 {
+	compatible = "nordic,nrf-twim";
+
+	status = "okay";
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-1 = <&i2c1_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-1 = <&uart0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_default>;
+	pinctrl-1 = <&pwm0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&spi4 {
+	compatible = "nordic,nrf-spim";
+	status = "okay";
+
+	pinctrl-0 = <&spi4_default>;
+	pinctrl-1 = <&spi4_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&qspi {
+	status = "okay";
+
+	pinctrl-0 = <&qspi_default>;
+	pinctrl-1 = <&qspi_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart1 {
+	compatible = "nordic,nrf-uarte";
+
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-1 = <&uart1_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&spi3 {
+	compatible = "nordic,nrf-spim";
+
+	cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&spi3_default>;
+	pinctrl-1 = <&spi3_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+zephyr_udc0: &usbd {
+	compatible = "nordic,nrf-usbd";
+
+	status = "okay";
+};
+
+/* Include default memory partition configuration file */
+#include <nordic/nrf5340_cpuapp_partition.dtsi>

boards/raytac/an7002q_db/nrf5340_cpuapp_common_pinctrl.dtsi

@@ -0,0 +1,128 @@
+&pinctrl {
+	i2c1_default: i2c1_default {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+				<NRF_PSEL(TWIM_SCL, 1, 3)>;
+		};
+	};
+
+	i2c1_sleep: i2c1_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+				<NRF_PSEL(TWIM_SCL, 1, 3)>;
+			low-power-enable;
+		};
+	};
+
+	uart0_default: uart0_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 20)>,
+				<NRF_PSEL(UART_RTS, 0, 19)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 22)>,
+				<NRF_PSEL(UART_CTS, 0, 21)>;
+			bias-pull-up;
+		};
+	};
+
+	uart0_sleep: uart0_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 20)>,
+				<NRF_PSEL(UART_RX, 0, 22)>,
+				<NRF_PSEL(UART_RTS, 0, 19)>,
+				<NRF_PSEL(UART_CTS, 0, 21)>;
+			low-power-enable;
+		};
+	};
+
+	pwm0_default: pwm0_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
+		};
+	};
+
+	pwm0_sleep: pwm0_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
+			low-power-enable;
+		};
+	};
+
+	qspi_default: qspi_default {
+		group1 {
+			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
+				<NRF_PSEL(QSPI_IO0, 0, 13)>,
+				<NRF_PSEL(QSPI_IO1, 0, 14)>,
+				<NRF_PSEL(QSPI_IO2, 0, 15)>,
+				<NRF_PSEL(QSPI_IO3, 0, 16)>,
+				<NRF_PSEL(QSPI_CSN, 0, 18)>;
+		};
+	};
+
+	qspi_sleep: qspi_sleep {
+		group1 {
+			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
+				<NRF_PSEL(QSPI_IO0, 0, 13)>,
+				<NRF_PSEL(QSPI_IO1, 0, 14)>,
+				<NRF_PSEL(QSPI_IO2, 0, 15)>,
+				<NRF_PSEL(QSPI_IO3, 0, 16)>,
+				<NRF_PSEL(QSPI_CSN, 0, 18)>;
+			low-power-enable;
+		};
+	};
+
+	uart1_default: uart1_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 1)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 0)>;
+			bias-pull-up;
+		};
+	};
+
+	uart1_sleep: uart1_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 1)>,
+				<NRF_PSEL(UART_RX, 1, 0)>;
+			low-power-enable;
+		};
+	};
+
+	spi3_default: spi3_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+				<NRF_PSEL(SPIM_MISO, 1, 14)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
+		};
+	};
+
+	spi3_sleep: spi3_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+				<NRF_PSEL(SPIM_MISO, 1, 14)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
+			low-power-enable;
+		};
+	};
+
+	spi4_default: spi4_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
+				<NRF_PSEL(SPIM_MISO, 0, 10)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 9)>;
+		};
+	};
+
+	spi4_sleep: spi4_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
+				<NRF_PSEL(SPIM_MISO, 0, 10)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 9)>;
+			low-power-enable;
+		};
+	};
+};

boards/raytac/an7002q_db/nrf70_common.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+iovdd-ctrl-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+bucken-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+host-irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+srrf-switch-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+
+wifi-max-tx-pwr-2g-dsss = <21>;
+wifi-max-tx-pwr-2g-mcs0 = <16>;
+wifi-max-tx-pwr-2g-mcs7 = <16>;
+
+wlan0: wlan {
+	compatible = "nordic,wlan";
+};

boards/raytac/an7002q_db/nrf70_common_5g.dtsi

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+wifi-max-tx-pwr-5g-low-mcs0 = <9>;
+wifi-max-tx-pwr-5g-low-mcs7 = <9>;
+wifi-max-tx-pwr-5g-mid-mcs0 = <11>;
+wifi-max-tx-pwr-5g-mid-mcs7 = <11>;
+wifi-max-tx-pwr-5g-high-mcs0 = <13>;
+wifi-max-tx-pwr-5g-high-mcs7 = <13>;

boards/raytac/an7002q_db/pre_dt_board.cmake

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
+# - flash-controller@39000 & kmu@39000
+# - power@5000 & clock@5000
+# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
+list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.dts

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Raytac Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
+#include "nrf5340_cpuapp_common.dtsi"
+#include "raytac_an7002q_db_nrf5340_cpuapp_pinctrl.dtsi"
+
+/ {
+	model = "Raytac AN7002-DB NRF5340 Application";
+	compatible = "raytac,raytac-an7002q-db-nrf5340-cpuapp";
+
+	chosen {
+		zephyr,sram = &sram0_image;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram-secure-partition = &sram0_s;
+		zephyr,sram-non-secure-partition = &sram0_ns;
+		zephyr,wifi = &wlan0;
+	};
+};
+
+&qspi {
+	nrf70: nrf7002@1 {
+		compatible = "nordic,nrf7002-qspi";
+		status = "okay";
+		reg = <1>;
+		qspi-frequency = <24000000>;
+		qspi-quad-mode;
+
+		#include "nrf70_common.dtsi"
+		#include "nrf70_common_5g.dtsi"
+	};
+};

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp.yaml

@@ -0,0 +1,19 @@
+identifier: raytac_an7002q_db/nrf5340/cpuapp
+name: Raytac-AN7002Q-DB-NRF5340-application-MCU
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+ram: 448
+flash: 1024
+supported:
+  - gpio
+  - i2c
+  - i2s
+  - pwm
+  - watchdog
+  - usbd
+  - usb_device
+  - netif:openthread
+vendor: raytac

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_defconfig

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable RNG
+CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG=y
+CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG_ALLOW_NON_CSPRNG=y
+
+# ISN needs CS-Rand which isn't supported upstream for nRF boards
+CONFIG_NET_TCP_ISN_RFC6528=n

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpuapp_pinctrl.dtsi

@@ -0,0 +1,18 @@
+&pinctrl {
+	spi2_default: spi2_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+				<NRF_PSEL(SPIM_MISO, 1, 14)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
+		};
+	};
+
+	spi2_sleep: spi2_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+				<NRF_PSEL(SPIM_MISO, 1, 14)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
+			low-power-enable;
+		};
+	};
+};

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.dts

@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Raytac Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpunet_qkaa.dtsi>
+#include "raytac_an7002q_db_nrf5340_cpunet_pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Raytac AN7002Q-DB NRF5340 Network";
+	compatible = "raytac,raytac-an7002q-db-nrf5340-cpunet";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-mcumgr = &uart0;
+		zephyr,bt-mon-uart = &uart0;
+		zephyr,bt-c2h-uart = &uart0;
+		zephyr,bt-hci-ipc = &ipc0;
+		nordic,802154-spinel-ipc = &ipc0;
+		zephyr,sram = &sram1;
+		zephyr,flash = &flash1;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,ieee802154 = &ieee802154;
+	};
+
+	leds {
+			compatible = "gpio-leds";
+
+			led0: led_0 {
+					gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+					label = "Green LED 0";
+			};
+
+			led1: led_1 {
+					gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+					label = "Green LED 1";
+			};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	nrf_radio_coex: coex {
+		status = "okay";
+		compatible = "nordic,nrf7002-coex";
+
+		req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+		status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+		grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
+		swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		bootloader-led0 = &led0;
+		mcuboot-button0 = &button0;
+		mcuboot-led0 = &led0;
+		watchdog0 = &wdt0;
+	};
+};
+
+&gpiote {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-1 = <&uart0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&i2c0 {
+	compatible = "nordic,nrf-twim";
+	/* Cannot be used together with uart0. */
+	/* status = "okay"; */
+
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-1 = <&i2c0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&spi0 {
+	compatible = "nordic,nrf-spim";
+	/* Cannot be used together with uart0. */
+	/* status = "okay"; */
+
+	cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-1 = <&spi0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&flash1 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0xc000>;
+		};
+
+		slot0_partition: partition@c000 {
+			label = "image-0";
+			reg = <0x0000C000 0x17000>;
+		};
+
+		slot1_partition: partition@23000 {
+			label = "image-1";
+			reg = <0x00023000 0x17000>;
+		};
+
+		storage_partition: partition@3a000 {
+			label = "storage";
+			reg = <0x0003a000 0x6000>;
+		};
+	};
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+/* Include default shared RAM configuration file */
+#include <vendor/nordic/nrf5340_shared_sram_partition.dtsi>

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet.yaml

@@ -0,0 +1,13 @@
+identifier: raytac_an7002q_db/nrf5340/cpunet
+name: Raytac AN7002Q-DB-NRF5340-network-MCU
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+ram: 64
+flash: 256
+supported:
+  - gpio
+  - watchdog
+vendor: raytac

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_defconfig

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/raytac/an7002q_db/raytac_an7002q_db_nrf5340_cpunet_pinctrl.dtsi

@@ -0,0 +1,56 @@
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 1)>,
+				<NRF_PSEL(UART_RTS, 1, 5)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 0)>,
+				<NRF_PSEL(UART_CTS, 1, 4)>;
+			bias-pull-up;
+		};
+	};
+
+	uart0_sleep: uart0_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 1)>,
+				<NRF_PSEL(UART_RX, 1, 0)>,
+				<NRF_PSEL(UART_RTS, 1, 5)>,
+				<NRF_PSEL(UART_CTS, 1, 4)>;
+			low-power-enable;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+				<NRF_PSEL(TWIM_SCL, 1, 3)>;
+		};
+	};
+
+	i2c0_sleep: i2c0_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+				<NRF_PSEL(TWIM_SCL, 1, 3)>;
+			low-power-enable;
+		};
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+				<NRF_PSEL(SPIM_MISO, 1, 14)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
+		};
+	};
+
+	spi0_sleep: spi0_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
+				<NRF_PSEL(SPIM_MISO, 1, 14)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
+			low-power-enable;
+		};
+	};
+};