Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
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/*
* Copyright (c) 2025 Pete Johanson
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <silabs/xg24/efr32mg24b220f1536im48.dtsi>
#include "xiao_mg24-pinctrl.dtsi"
#include "seeed_xiao_connector.dtsi"
/ {
model = "Seeed XIAO MG24";
compatible = "seeed,xiao_mg24", "silabs,efr32mg24";
chosen {
zephyr,bt-hci = &bt_hci_silabs;
zephyr,code-partition = &slot0_partition;
zephyr,console = &usart0;
zephyr,flash = &flash0;
zephyr,shell-uart = &usart0;
zephyr,sram = &sram0;
zephyr,uart-pipe = &usart0;
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
watchdog0 = &wdog0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpioa 7 GPIO_ACTIVE_LOW>;
label = "LED 0";
};
};
};
&cpu0 {
clock-frequency = <78000000>;
};
&pstate_em3 {
status = "disabled";
};
&hfxo {
ctune = <95>;
precision = <50>;
status = "okay";
};
&lfxo {
ctune = <44>;
precision = <50>;
status = "okay";
};
&hfrcodpll {
clock-frequency = <DT_FREQ_M(78)>;
clocks = <&hfxo>;
dpll-autorecover;
dpll-edge = "fall";
dpll-lock = "phase";
dpll-m = <1919>;
dpll-n = <3839>;
};
&em23grpaclk {
clocks = <&lfxo>;
};
&em4grpaclk {
clocks = <&lfxo>;
};
&sysrtcclk {
clocks = <&lfxo>;
};
&wdog0clk {
clocks = <&lfxo>;
};
&wdog1clk {
clocks = <&lfxo>;
};
&usart0 {
current-speed = <115200>;
pinctrl-0 = <&usart0_default>;
pinctrl-names = "default";
status = "okay";
};
&eusart0 {
compatible = "silabs,eusart-uart";
current-speed = <115200>;
pinctrl-0 = <&eusart0_default>;
pinctrl-names = "default";
};
&eusart1 {
compatible = "silabs,eusart-spi";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <4000000>;
cs-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&eusart1_default>;
pinctrl-names = "default";
};
&i2c0 {
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
&gpio {
location-swo = <0>;
status = "okay";
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
rf_sw: rf_sw {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
};
rf_sw_enable: rf_sw_enable {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&wdog0 {
status = "okay";
};
&sysrtc0 {
status = "okay";
};
&se {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 48 kB for the bootloader */
boot_partition: partition@0 {
reg = <0x0 DT_SIZE_K(48)>;
label = "mcuboot";
read-only;
};
/* Reserve 720 kB for the application in slot 0 */
slot0_partition: partition@c000 {
reg = <0x0000c000 0x000B8000>;
label = "image-0";
};
/* Reserve 720 kB for the application in slot 1 */
slot1_partition: partition@C4000 {
reg = <0x000C0000 0x000B8000>;
label = "image-1";
};
/* Set 16 kB of storage at the end of the 1536 kB of flash */
storage_partition: partition@17c000 {
reg = <0x0017c000 DT_SIZE_K(16)>;
label = "storage";
};
};
};
&bt_hci_silabs {
status = "okay";
};