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89 lines
2.3 KiB
89 lines
2.3 KiB
/* |
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* Copyright (c) 2023 Google LLC |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <clock_control/clock_stm32_ll_common.h> |
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#include <soc.h> |
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#include <stm32f4xx_ll_bus.h> |
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#include <stm32f4xx_ll_cortex.h> |
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#include <stm32f4xx_ll_pwr.h> |
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#include <stm32f4xx.h> |
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#include <zephyr/drivers/clock_control/stm32_clock_control.h> |
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#include <zephyr/drivers/counter.h> |
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#include <zephyr/drivers/interrupt_controller/gic.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/logging/log.h> |
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#include <zephyr/pm/pm.h> |
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#include <zephyr/init.h> |
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL); |
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BUILD_ASSERT(DT_SAME_NODE(DT_CHOSEN(zephyr_cortex_m_idle_timer), DT_NODELABEL(rtc)), |
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"STM32Fx series needs RTC as an additional IDLE timer for power management"); |
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void pm_state_set(enum pm_state state, uint8_t substate_id) |
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{ |
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ARG_UNUSED(substate_id); |
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switch (state) { |
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case PM_STATE_SUSPEND_TO_IDLE: |
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LL_LPM_DisableEventOnPend(); |
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LL_PWR_ClearFlag_WU(); |
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/* According to datasheet (DS11139 Rev 8,Table 38.), wakeup with regulator in |
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* low-power mode takes typically 8us, max 13us more time than with the main |
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* regulator. We are using RTC as a wakeup source, which has a tick 62,5us. |
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* It means we have to add significant margin to the exit-latency anyway, |
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* so it is worth always using the low-power regulator. |
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*/ |
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LL_PWR_SetPowerMode(LL_PWR_MODE_STOP_LPREGU); |
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LL_LPM_EnableDeepSleep(); |
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k_cpu_idle(); |
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break; |
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default: |
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LOG_DBG("Unsupported power state %u", state); |
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break; |
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} |
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} |
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) |
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{ |
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ARG_UNUSED(substate_id); |
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switch (state) { |
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case PM_STATE_SUSPEND_TO_IDLE: |
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LL_LPM_DisableSleepOnExit(); |
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LL_LPM_EnableSleep(); |
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/* Restore the clock setup. */ |
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stm32_clock_control_init(NULL); |
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break; |
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default: |
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LOG_DBG("Unsupported power substate-id %u", state); |
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break; |
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} |
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/* |
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* System is now in active mode. Reenable interrupts which were |
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* disabled when OS started idling code. |
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*/ |
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irq_unlock(0); |
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} |
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static int stm32_power_init(void) |
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{ |
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/* Enable Power clock. It should by done by default, but make sure to |
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* enable it for all STM32F4x chips. |
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*/ |
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); |
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/* Enabling debug during STOP mode is done by the common STM32 configuration */ |
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return 0; |
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} |
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SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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