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47 lines
1.2 KiB
47 lines
1.2 KiB
/* |
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* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** |
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* @file |
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* @brief System/hardware module for STM32L0 processor |
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*/ |
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#include <zephyr/device.h> |
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#include <zephyr/init.h> |
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#include <zephyr/linker/linker-defs.h> |
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#include <string.h> |
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#include <stm32_ll_bus.h> |
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#include <stm32_ll_system.h> |
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#include <cmsis_core.h> |
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/** |
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* @brief Perform basic hardware initialization at boot. |
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* |
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* This needs to be run from the very beginning. |
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*/ |
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void soc_early_init_hook(void) |
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{ |
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/* Enable ART accelerator prefetch */ |
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LL_FLASH_EnablePrefetch(); |
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/* Update CMSIS SystemCoreClock variable (HCLK) */ |
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/* At reset, system core clock is set to 2.1 MHz from MSI */ |
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SystemCoreClock = 2097152; |
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/* On STM32L0, there are some hardfault when enabling DBGMCU bit: |
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* Sleep, Stop or Standby. |
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* See https://github.com/zephyrproject-rtos/zephyr/issues/#37119 |
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* For unclear reason, enabling DMA clock fixes this issue |
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* (similarly than it fixes |
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* https://github.com/zephyrproject-rtos/zephyr/issues/#34324 ) |
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*/ |
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); |
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#ifdef CONFIG_PM |
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/* Enable Power clock */ |
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); |
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#endif |
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}
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