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193 lines
4.1 KiB
193 lines
4.1 KiB
/* |
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** |
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* @brief Driver for Nuclie's Extended Core Interrupt Controller |
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*/ |
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#include <zephyr/kernel.h> |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/device.h> |
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#include <zephyr/sw_isr_table.h> |
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#include <zephyr/drivers/interrupt_controller/riscv_clic.h> |
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#define DT_DRV_COMPAT nuclei_eclic |
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union CLICCFG { |
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struct { |
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uint8_t _reserved0 : 1; |
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/** number of interrupt level bits */ |
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uint8_t nlbits : 4; |
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uint8_t _reserved1 : 2; |
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uint8_t _reserved2 : 1; |
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} b; |
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uint8_t w; |
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}; |
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union CLICINFO { |
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struct { |
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/** number of max supported interrupts */ |
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uint32_t numint : 13; |
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/** architecture version */ |
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uint32_t version : 8; |
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/** supported bits in the clicintctl */ |
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uint32_t intctlbits : 4; |
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uint32_t _reserved0 : 7; |
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} b; |
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uint32_t qw; |
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}; |
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union CLICMTH { |
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uint8_t w; |
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}; |
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union CLICINTIP { |
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struct { |
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/** Interrupt Pending */ |
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uint8_t IP : 1; |
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uint8_t reserved0 : 7; |
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} b; |
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uint8_t w; |
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}; |
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union CLICINTIE { |
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struct { |
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/** Interrupt Enabled */ |
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uint8_t IE : 1; |
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uint8_t reserved0 : 7; |
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} b; |
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uint8_t w; |
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}; |
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union CLICINTATTR { |
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struct { |
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/** 0: non-vectored 1:vectored */ |
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uint8_t shv : 1; |
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/** 0: level 1: rising edge 2: falling edge */ |
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uint8_t trg : 2; |
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uint8_t reserved0 : 3; |
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uint8_t reserved1 : 2; |
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} b; |
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uint8_t w; |
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}; |
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struct CLICCTRL { |
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volatile union CLICINTIP INTIP; |
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volatile union CLICINTIE INTIE; |
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volatile union CLICINTATTR INTATTR; |
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volatile uint8_t INTCTRL; |
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}; |
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/** CLIC INTATTR: TRIG Mask */ |
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#define CLIC_INTATTR_TRIG_Msk 0x3U |
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#define ECLIC_CFG (*((volatile union CLICCFG *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 0)))) |
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#define ECLIC_INFO (*((volatile union CLICINFO *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 1)))) |
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#define ECLIC_MTH (*((volatile union CLICMTH *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 2)))) |
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#define ECLIC_CTRL ((volatile struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3))) |
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#define ECLIC_CTRL_SIZE (DT_REG_SIZE_BY_IDX(DT_NODELABEL(eclic), 3)) |
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static uint8_t nlbits; |
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static uint8_t intctlbits; |
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static uint8_t max_prio; |
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static uint8_t max_level; |
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static uint8_t intctrl_mask; |
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static inline uint8_t leftalign8(uint8_t val, uint8_t shift) |
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{ |
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return (val << (8U - shift)); |
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} |
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static inline uint8_t mask8(uint8_t len) |
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{ |
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return ((1 << len) - 1) & 0xFFFFU; |
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} |
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/** |
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* @brief Enable interrupt |
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*/ |
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void riscv_clic_irq_enable(uint32_t irq) |
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{ |
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ECLIC_CTRL[irq].INTIE.b.IE = 1; |
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} |
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/** |
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* @brief Disable interrupt |
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*/ |
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void riscv_clic_irq_disable(uint32_t irq) |
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{ |
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ECLIC_CTRL[irq].INTIE.b.IE = 0; |
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} |
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/** |
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* @brief Get enable status of interrupt |
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*/ |
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int riscv_clic_irq_is_enabled(uint32_t irq) |
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{ |
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return ECLIC_CTRL[irq].INTIE.b.IE; |
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} |
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/** |
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* @brief Set priority and level of interrupt |
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*/ |
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void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags) |
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{ |
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const uint8_t prio = leftalign8(MIN(pri, max_prio), intctlbits); |
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const uint8_t level = leftalign8(max_level, nlbits); |
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const uint8_t intctrl = (prio | level) | (~intctrl_mask); |
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ECLIC_CTRL[irq].INTCTRL = intctrl; |
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union CLICINTATTR intattr = {.w = 0}; |
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/* Set non-vectoring as default. */ |
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intattr.b.shv = 0; |
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intattr.b.trg = (uint8_t)(flags & CLIC_INTATTR_TRIG_Msk); |
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ECLIC_CTRL[irq].INTATTR = intattr; |
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} |
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/** |
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* @brief Set vector mode of interrupt |
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*/ |
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void riscv_clic_irq_vector_set(uint32_t irq) |
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{ |
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/* Set Selective Hardware Vectoring. */ |
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union CLICINTATTR intattr = ECLIC_CTRL[irq].INTATTR; |
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intattr.b.shv = 1; |
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ECLIC_CTRL[irq].INTATTR = intattr; |
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} |
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/** |
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* @brief Set pending bit of an interrupt |
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*/ |
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void riscv_clic_irq_set_pending(uint32_t irq) |
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{ |
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ECLIC_CTRL[irq].INTIP.b.IP = 1; |
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} |
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static int nuclei_eclic_init(const struct device *dev) |
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{ |
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ECLIC_MTH.w = 0; |
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ECLIC_CFG.w = 0; |
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ECLIC_CFG.b.nlbits = 0; |
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for (int i = 0; i < ECLIC_CTRL_SIZE; i++) { |
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ECLIC_CTRL[i] = (struct CLICCTRL) { 0 }; |
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} |
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nlbits = ECLIC_CFG.b.nlbits; |
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intctlbits = ECLIC_INFO.b.intctlbits; |
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max_prio = mask8(intctlbits - nlbits); |
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max_level = mask8(nlbits); |
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intctrl_mask = leftalign8(mask8(intctlbits), intctlbits); |
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return 0; |
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} |
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DEVICE_DT_INST_DEFINE(0, nuclei_eclic_init, NULL, NULL, NULL, |
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PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
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