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103 lines
2.3 KiB
103 lines
2.3 KiB
/* |
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* |
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* Copyright (c) 2017 Linaro Limited. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <soc.h> |
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#include <stm32_ll_bus.h> |
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#include <stm32_ll_pwr.h> |
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#include <stm32_ll_rcc.h> |
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#include <stm32_ll_utils.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/drivers/clock_control/stm32_clock_control.h> |
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#include <zephyr/sys/time_units.h> |
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#include "clock_stm32_ll_common.h" |
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#if defined(STM32_PLL_ENABLED) |
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#if defined(LL_RCC_MSIRANGESEL_RUN) |
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#define CALC_RUN_MSI_FREQ(range) __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, \ |
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range << RCC_CR_MSIRANGE_Pos); |
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#else |
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#define CALC_RUN_MSI_FREQ(range) __LL_RCC_CALC_MSI_FREQ(range << RCC_CR_MSIRANGE_Pos); |
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#endif |
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/** |
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* @brief Return PLL source |
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*/ |
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__unused |
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static uint32_t get_pll_source(void) |
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{ |
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/* Configure PLL source */ |
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) { |
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return LL_RCC_PLLSOURCE_HSI; |
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) { |
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return LL_RCC_PLLSOURCE_HSE; |
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} else if (IS_ENABLED(STM32_PLL_SRC_MSI)) { |
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return LL_RCC_PLLSOURCE_MSI; |
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} |
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__ASSERT(0, "Invalid source"); |
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return 0; |
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} |
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/** |
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* @brief get the pll source frequency |
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*/ |
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__unused |
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uint32_t get_pllsrc_frequency(void) |
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{ |
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) { |
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return STM32_HSI_FREQ; |
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) { |
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return STM32_HSE_FREQ; |
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#if defined(STM32_MSI_ENABLED) |
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} else if (IS_ENABLED(STM32_PLL_SRC_MSI)) { |
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return CALC_RUN_MSI_FREQ(STM32_MSI_RANGE); |
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#endif |
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} |
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__ASSERT(0, "Invalid source"); |
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return 0; |
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} |
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/** |
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* @brief Set up pll configuration |
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*/ |
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void config_pll_sysclock(void) |
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{ |
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#ifdef PWR_CR5_R1MODE |
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/* set power boost mode for sys clock greater than 80MHz */ |
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if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) { |
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LL_PWR_EnableRange1BoostMode(); |
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} |
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#endif /* PWR_CR5_R1MODE */ |
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LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(), |
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pllm(STM32_PLL_M_DIVISOR), |
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STM32_PLL_N_MULTIPLIER, |
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pllr(STM32_PLL_R_DIVISOR)); |
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LL_RCC_PLL_EnableDomain_SYS(); |
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} |
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#endif /* defined(STM32_PLL_ENABLED) */ |
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/** |
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* @brief Activate default clocks |
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*/ |
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void config_enable_default_clocks(void) |
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{ |
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#ifdef LL_APB1_GRP1_PERIPH_PWR |
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/* Enable the power interface clock */ |
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) |
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/* HW semaphore Clock enable */ |
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM); |
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#endif |
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}
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