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112 lines
2.6 KiB
112 lines
2.6 KiB
/* |
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* Copyright (c) 2019 Vestas Wind Systems A/S |
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* |
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* Based on clock_control_mcux_sim.c, which is: |
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* Copyright (c) 2017, NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <drivers/clock_control.h> |
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#include <dt-bindings/clock/kinetis_scg.h> |
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#include <soc.h> |
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#include <fsl_clock.h> |
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL |
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#include <logging/log.h> |
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LOG_MODULE_REGISTER(clock_control_scg); |
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static int mcux_scg_on(struct device *dev, clock_control_subsys_t sub_system) |
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{ |
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return 0; |
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} |
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static int mcux_scg_off(struct device *dev, clock_control_subsys_t sub_system) |
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{ |
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return 0; |
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} |
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static int mcux_scg_get_rate(struct device *dev, |
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clock_control_subsys_t sub_system, |
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u32_t *rate) |
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{ |
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clock_name_t clock_name; |
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switch ((u32_t) sub_system) { |
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case KINETIS_SCG_CORESYS_CLK: |
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clock_name = kCLOCK_CoreSysClk; |
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break; |
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case KINETIS_SCG_BUS_CLK: |
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clock_name = kCLOCK_BusClk; |
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break; |
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case KINETIS_SCG_FLEXBUS_CLK: |
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clock_name = kCLOCK_FlexBusClk; |
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break; |
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case KINETIS_SCG_FLASH_CLK: |
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clock_name = kCLOCK_FlashClk; |
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break; |
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case KINETIS_SCG_SOSC_CLK: |
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clock_name = kCLOCK_ScgSysOscClk; |
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break; |
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case KINETIS_SCG_SIRC_CLK: |
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clock_name = kCLOCK_ScgSircClk; |
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break; |
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case KINETIS_SCG_FIRC_CLK: |
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clock_name = kCLOCK_ScgFircClk; |
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break; |
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case KINETIS_SCG_SPLL_CLK: |
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clock_name = kCLOCK_ScgSysPllClk; |
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break; |
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case KINETIS_SCG_SOSC_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgSysOscAsyncDiv1Clk; |
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break; |
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case KINETIS_SCG_SOSC_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgSysOscAsyncDiv2Clk; |
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break; |
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case KINETIS_SCG_SIRC_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgSircAsyncDiv1Clk; |
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break; |
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case KINETIS_SCG_SIRC_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgSircAsyncDiv2Clk; |
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break; |
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case KINETIS_SCG_FIRC_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgFircAsyncDiv1Clk; |
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break; |
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case KINETIS_SCG_FIRC_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgFircAsyncDiv2Clk; |
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break; |
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case KINETIS_SCG_SPLL_ASYNC_DIV1_CLK: |
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clock_name = kCLOCK_ScgSysPllAsyncDiv1Clk; |
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break; |
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case KINETIS_SCG_SPLL_ASYNC_DIV2_CLK: |
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clock_name = kCLOCK_ScgSysPllAsyncDiv2Clk; |
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break; |
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default: |
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LOG_ERR("Unsupported clock name"); |
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return -EINVAL; |
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} |
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*rate = CLOCK_GetFreq(clock_name); |
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return 0; |
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} |
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static int mcux_scg_init(struct device *dev) |
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{ |
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#ifdef DT_INST_0_NXP_KINETIS_SCG_CLKOUT_SOURCE |
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CLOCK_SetClkOutSel(DT_INST_0_NXP_KINETIS_SCG_CLKOUT_SOURCE); |
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#endif |
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return 0; |
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} |
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static const struct clock_control_driver_api mcux_scg_driver_api = { |
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.on = mcux_scg_on, |
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.off = mcux_scg_off, |
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.get_rate = mcux_scg_get_rate, |
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}; |
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DEVICE_AND_API_INIT(mcux_scg, DT_INST_0_NXP_KINETIS_SCG_LABEL, |
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&mcux_scg_init, |
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NULL, NULL, |
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, |
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&mcux_scg_driver_api);
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