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339 lines
7.8 KiB
339 lines
7.8 KiB
/* |
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* Copyright (c) 2018 omSquare s.r.o. |
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* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT atmel_sam0_rtc |
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/** |
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* @file |
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* @brief Atmel SAM0 series RTC-based system timer |
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* |
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* This system timer implementation supports both tickless and ticking modes. |
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* In tickless mode, RTC counts continually in 32-bit mode and timeouts are |
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* scheduled using the RTC comparator. In ticking mode, RTC is configured to |
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* generate an interrupt every tick. |
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*/ |
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#include <zephyr/init.h> |
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#include <soc.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/timer/system_timer.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/sys_clock.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/sys/util.h> |
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/* clang-format off */ |
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/* RTC registers. */ |
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#define RTC0 ((RtcMode0 *) DT_INST_REG_ADDR(0)) |
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#ifdef MCLK |
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#define RTC_CLOCK_HW_CYCLES_PER_SEC SOC_ATMEL_SAM0_OSC32K_FREQ_HZ |
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#else |
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#define RTC_CLOCK_HW_CYCLES_PER_SEC SOC_ATMEL_SAM0_GCLK0_FREQ_HZ |
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#endif |
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/* Number of sys timer cycles per on tick. */ |
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#define CYCLES_PER_TICK (RTC_CLOCK_HW_CYCLES_PER_SEC \ |
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC) |
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/* Maximum number of ticks. */ |
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#define MAX_TICKS (UINT32_MAX / CYCLES_PER_TICK - 2) |
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#ifdef CONFIG_TICKLESS_KERNEL |
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/* |
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* Due to the nature of clock synchronization, reading from or writing to some |
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* RTC registers takes approximately six RTC_GCLK cycles. This constant defines |
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* a safe threshold for the comparator. |
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*/ |
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#define TICK_THRESHOLD 7 |
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BUILD_ASSERT(CYCLES_PER_TICK > TICK_THRESHOLD, |
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"CYCLES_PER_TICK must be greater than TICK_THRESHOLD for " |
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"tickless mode"); |
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#else /* !CONFIG_TICKLESS_KERNEL */ |
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/* |
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* For some reason, RTC does not generate interrupts when COMP == 0, |
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* MATCHCLR == 1 and PRESCALER == 0. So we need to check that CYCLES_PER_TICK |
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* is more than one. |
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*/ |
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BUILD_ASSERT(CYCLES_PER_TICK > 1, |
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"CYCLES_PER_TICK must be greater than 1 for ticking mode"); |
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#endif /* CONFIG_TICKLESS_KERNEL */ |
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/* Tick/cycle count of the last announce call. */ |
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static volatile uint32_t rtc_last; |
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#ifndef CONFIG_TICKLESS_KERNEL |
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/* Current tick count. */ |
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static volatile uint32_t rtc_counter; |
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/* Tick value of the next timeout. */ |
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static volatile uint32_t rtc_timeout; |
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PINCTRL_DT_INST_DEFINE(0); |
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static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0); |
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#endif /* CONFIG_TICKLESS_KERNEL */ |
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/* |
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* Waits for RTC bus synchronization. |
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*/ |
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static inline void rtc_sync(void) |
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{ |
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/* Wait for bus synchronization... */ |
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#ifdef RTC_STATUS_SYNCBUSY |
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while (RTC0->STATUS.reg & RTC_STATUS_SYNCBUSY) { |
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} |
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#else |
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while (RTC0->SYNCBUSY.reg) { |
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} |
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#endif |
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} |
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/* |
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* Reads RTC COUNT register. First a read request must be written to READREQ, |
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* then - when bus synchronization completes - the COUNT register is read and |
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* returned. |
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*/ |
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static uint32_t rtc_count(void) |
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{ |
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#ifdef RTC_READREQ_RREQ |
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RTC0->READREQ.reg = RTC_READREQ_RREQ; |
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#endif |
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rtc_sync(); |
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return RTC0->COUNT.reg; |
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} |
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static void rtc_reset(void) |
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{ |
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rtc_sync(); |
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/* Disable interrupt. */ |
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RTC0->INTENCLR.reg = RTC_MODE0_INTENCLR_MASK; |
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/* Clear interrupt flag. */ |
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RTC0->INTFLAG.reg = RTC_MODE0_INTFLAG_MASK; |
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/* Disable RTC module. */ |
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#ifdef RTC_MODE0_CTRL_ENABLE |
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RTC0->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; |
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#else |
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RTC0->CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; |
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#endif |
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rtc_sync(); |
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/* Initiate software reset. */ |
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#ifdef RTC_MODE0_CTRL_SWRST |
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RTC0->CTRL.bit.SWRST = 1; |
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while (RTC0->CTRL.bit.SWRST) { |
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} |
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#else |
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RTC0->CTRLA.bit.SWRST = 1; |
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while (RTC0->CTRLA.bit.SWRST) { |
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} |
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#endif |
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} |
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static void rtc_isr(const void *arg) |
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{ |
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ARG_UNUSED(arg); |
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/* Read and clear the interrupt flag register. */ |
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uint16_t status = RTC0->INTFLAG.reg; |
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RTC0->INTFLAG.reg = status; |
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#ifdef CONFIG_TICKLESS_KERNEL |
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/* Read the current counter and announce the elapsed time in ticks. */ |
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uint32_t count = rtc_count(); |
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if (count != rtc_last) { |
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uint32_t ticks = (count - rtc_last) / CYCLES_PER_TICK; |
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sys_clock_announce(ticks); |
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rtc_last += ticks * CYCLES_PER_TICK; |
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} |
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#else /* !CONFIG_TICKLESS_KERNEL */ |
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if (status) { |
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/* RTC just ticked one more tick... */ |
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if (++rtc_counter == rtc_timeout) { |
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sys_clock_announce(rtc_counter - rtc_last); |
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rtc_last = rtc_counter; |
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} |
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} else { |
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/* ISR was invoked directly from sys_clock_set_timeout. */ |
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sys_clock_announce(0); |
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} |
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#endif /* CONFIG_TICKLESS_KERNEL */ |
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} |
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void sys_clock_set_timeout(int32_t ticks, bool idle) |
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{ |
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ARG_UNUSED(idle); |
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#ifdef CONFIG_TICKLESS_KERNEL |
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ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks; |
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ticks = CLAMP(ticks - 1, 0, (int32_t) MAX_TICKS); |
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/* Compute number of RTC cycles until the next timeout. */ |
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uint32_t count = rtc_count(); |
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uint32_t timeout = ticks * CYCLES_PER_TICK + count % CYCLES_PER_TICK; |
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/* Round to the nearest tick boundary. */ |
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timeout = DIV_ROUND_UP(timeout, CYCLES_PER_TICK) * CYCLES_PER_TICK; |
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if (timeout < TICK_THRESHOLD) { |
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timeout += CYCLES_PER_TICK; |
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} |
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rtc_sync(); |
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RTC0->COMP[0].reg = count + timeout; |
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#else /* !CONFIG_TICKLESS_KERNEL */ |
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if (ticks == K_TICKS_FOREVER) { |
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/* Disable comparator for K_TICKS_FOREVER and other negative |
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* values. |
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*/ |
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rtc_timeout = rtc_counter; |
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return; |
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} |
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if (ticks < 1) { |
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ticks = 1; |
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} |
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/* Avoid race condition between reading counter and ISR incrementing |
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* it. |
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*/ |
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unsigned int key = irq_lock(); |
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rtc_timeout = rtc_counter + ticks; |
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irq_unlock(key); |
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#endif /* CONFIG_TICKLESS_KERNEL */ |
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} |
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uint32_t sys_clock_elapsed(void) |
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{ |
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#ifdef CONFIG_TICKLESS_KERNEL |
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return (rtc_count() - rtc_last) / CYCLES_PER_TICK; |
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#else |
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return rtc_counter - rtc_last; |
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#endif |
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} |
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uint32_t sys_clock_cycle_get_32(void) |
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{ |
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/* Just return the absolute value of RTC cycle counter. */ |
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return rtc_count(); |
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} |
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#define ASSIGNED_CLOCKS_CELL_BY_NAME \ |
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ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME |
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static int sys_clock_driver_init(void) |
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{ |
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volatile uint32_t *mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(0); |
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uint32_t mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(0, bit); |
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*mclk |= mclk_mask; |
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#ifdef MCLK |
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K; |
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#else |
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN |
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| GCLK_CLKCTRL_GEN(ASSIGNED_CLOCKS_CELL_BY_NAME(0, gclk, gen)) |
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| GCLK_CLKCTRL_ID(DT_INST_CLOCKS_CELL_BY_NAME(0, gclk, id)); |
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/* Synchronize GCLK. */ |
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while (GCLK->STATUS.bit.SYNCBUSY) { |
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} |
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#endif |
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#ifndef CONFIG_TICKLESS_KERNEL |
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int retval = pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT); |
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if (retval < 0 && retval != -ENOENT) { |
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return retval; |
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} |
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#endif |
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/* Reset module to hardware defaults. */ |
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rtc_reset(); |
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rtc_last = 0U; |
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/* Configure RTC with 32-bit mode, configured prescaler and MATCHCLR. */ |
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#ifdef RTC_MODE0_CTRL_MODE |
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uint16_t ctrl = RTC_MODE0_CTRL_MODE(0) | RTC_MODE0_CTRL_PRESCALER(0); |
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#else |
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uint16_t ctrl = RTC_MODE0_CTRLA_MODE(0) | RTC_MODE0_CTRLA_PRESCALER(0); |
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#endif |
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#ifdef RTC_MODE0_CTRLA_COUNTSYNC |
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ctrl |= RTC_MODE0_CTRLA_COUNTSYNC; |
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#endif |
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#ifndef CONFIG_TICKLESS_KERNEL |
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#ifdef RTC_MODE0_CTRL_MATCHCLR |
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ctrl |= RTC_MODE0_CTRL_MATCHCLR; |
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#else |
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ctrl |= RTC_MODE0_CTRLA_MATCHCLR; |
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#endif |
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#endif |
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rtc_sync(); |
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#ifdef RTC_MODE0_CTRL_MODE |
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RTC0->CTRL.reg = ctrl; |
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#else |
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RTC0->CTRLA.reg = ctrl; |
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#endif |
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#ifdef CONFIG_TICKLESS_KERNEL |
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/* Tickless kernel lets RTC count continually and ignores overflows. */ |
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RTC0->INTENSET.reg = RTC_MODE0_INTENSET_CMP0; |
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#else |
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/* Non-tickless mode uses comparator together with MATCHCLR. */ |
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rtc_sync(); |
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RTC0->COMP[0].reg = CYCLES_PER_TICK; |
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RTC0->INTENSET.reg = RTC_MODE0_INTENSET_OVF; |
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rtc_counter = 0U; |
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rtc_timeout = 0U; |
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#endif |
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/* Enable RTC module. */ |
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rtc_sync(); |
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#ifdef RTC_MODE0_CTRL_ENABLE |
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RTC0->CTRL.reg |= RTC_MODE0_CTRL_ENABLE; |
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#else |
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RTC0->CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; |
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#endif |
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/* Enable RTC interrupt. */ |
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NVIC_ClearPendingIRQ(DT_INST_IRQN(0)); |
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IRQ_CONNECT(DT_INST_IRQN(0), |
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DT_INST_IRQ(0, priority), rtc_isr, 0, 0); |
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irq_enable(DT_INST_IRQN(0)); |
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return 0; |
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} |
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, |
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY); |
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/* clang-format on */
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