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283 lines
8.8 KiB
283 lines
8.8 KiB
/* |
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* Copyright (c) 2016 Piotr Mienkowski |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** @file |
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* @brief Atmel SAM MCU family Ethernet MAC (GMAC) driver. |
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*/ |
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#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SAM_GMAC_PRIV_H_ |
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#define ZEPHYR_DRIVERS_ETHERNET_ETH_SAM_GMAC_PRIV_H_ |
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#include <zephyr/types.h> |
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#define ATMEL_OUI_B0 0x00 |
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#define ATMEL_OUI_B1 0x04 |
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#define ATMEL_OUI_B2 0x25 |
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/* This option enables support to push multiple packets to the DMA engine. |
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* This currently doesn't work given the current version of net_pkt or |
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* net_buf does not allowed access from multiple threads. This option is |
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* therefore currently disabled. |
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*/ |
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#define GMAC_MULTIPLE_TX_PACKETS 0 |
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#define GMAC_MTU NET_ETH_MTU |
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#define GMAC_FRAME_SIZE_MAX (GMAC_MTU + 18) |
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/** Cache alignment */ |
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#define GMAC_DCACHE_ALIGNMENT 32 |
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/** Memory alignment of the RX/TX Buffer Descriptor List */ |
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#define GMAC_DESC_ALIGNMENT 4 |
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/** Total number of queues supported by GMAC hardware module */ |
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#define GMAC_QUEUE_NUM DT_INST_PROP(0, num_queues) |
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#define GMAC_PRIORITY_QUEUE_NUM (GMAC_QUEUE_NUM - 1) |
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#if (GMAC_PRIORITY_QUEUE_NUM >= 1) |
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BUILD_ASSERT(ARRAY_SIZE(GMAC->GMAC_TBQBAPQ) + 1 == GMAC_QUEUE_NUM, |
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"GMAC_QUEUE_NUM doesn't match soc header"); |
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#endif |
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/** Number of priority queues used */ |
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#define GMAC_ACTIVE_QUEUE_NUM (CONFIG_ETH_SAM_GMAC_QUEUES) |
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#define GMAC_ACTIVE_PRIORITY_QUEUE_NUM (GMAC_ACTIVE_QUEUE_NUM - 1) |
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/** RX descriptors count for main queue */ |
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#define MAIN_QUEUE_RX_DESC_COUNT (CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT + 1) |
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/** TX descriptors count for main queue */ |
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#define MAIN_QUEUE_TX_DESC_COUNT (CONFIG_NET_BUF_TX_COUNT + 1) |
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/** RX/TX descriptors count for priority queues */ |
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#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1 |
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#define PRIORITY_QUEUE1_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT |
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#define PRIORITY_QUEUE1_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT |
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#else |
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#define PRIORITY_QUEUE1_RX_DESC_COUNT 1 |
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#define PRIORITY_QUEUE1_TX_DESC_COUNT 1 |
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#endif |
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#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2 |
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#define PRIORITY_QUEUE2_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT |
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#define PRIORITY_QUEUE2_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT |
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#else |
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#define PRIORITY_QUEUE2_RX_DESC_COUNT 1 |
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#define PRIORITY_QUEUE2_TX_DESC_COUNT 1 |
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#endif |
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#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3 |
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#define PRIORITY_QUEUE3_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT |
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#define PRIORITY_QUEUE3_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT |
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#else |
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#define PRIORITY_QUEUE3_RX_DESC_COUNT 1 |
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#define PRIORITY_QUEUE3_TX_DESC_COUNT 1 |
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#endif |
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#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4 |
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#define PRIORITY_QUEUE4_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT |
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#define PRIORITY_QUEUE4_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT |
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#else |
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#define PRIORITY_QUEUE4_RX_DESC_COUNT 1 |
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#define PRIORITY_QUEUE4_TX_DESC_COUNT 1 |
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#endif |
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#if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5 |
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#define PRIORITY_QUEUE5_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT |
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#define PRIORITY_QUEUE5_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT |
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#else |
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#define PRIORITY_QUEUE5_RX_DESC_COUNT 1 |
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#define PRIORITY_QUEUE5_TX_DESC_COUNT 1 |
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#endif |
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/* |
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* Receive buffer descriptor bit field definitions |
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*/ |
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/** Buffer ownership, needs to be 0 for the GMAC to write data to the buffer */ |
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#define GMAC_RXW0_OWNERSHIP (0x1u << 0) |
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/** Last descriptor in the receive buffer descriptor list */ |
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#define GMAC_RXW0_WRAP (0x1u << 1) |
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/** Address of beginning of buffer */ |
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#define GMAC_RXW0_ADDR (0x3FFFFFFFu << 2) |
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/** Receive frame length including FCS */ |
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#define GMAC_RXW1_LEN (0x1FFFu << 0) |
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/** FCS status */ |
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#define GMAC_RXW1_FCS_STATUS (0x1u << 13) |
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/** Start of frame */ |
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#define GMAC_RXW1_SOF (0x1u << 14) |
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/** End of frame */ |
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#define GMAC_RXW1_EOF (0x1u << 15) |
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/** Canonical Format Indicator */ |
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#define GMAC_RXW1_CFI (0x1u << 16) |
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/** VLAN priority (if VLAN detected) */ |
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#define GMAC_RXW1_VLANPRIORITY (0x7u << 17) |
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/** Priority tag detected */ |
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#define GMAC_RXW1_PRIORITYDETECTED (0x1u << 20) |
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/** VLAN tag detected */ |
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#define GMAC_RXW1_VLANDETECTED (0x1u << 21) |
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/** Type ID match */ |
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#define GMAC_RXW1_TYPEIDMATCH (0x3u << 22) |
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/** Type ID register match found */ |
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#define GMAC_RXW1_TYPEIDFOUND (0x1u << 24) |
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/** Specific Address Register match */ |
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#define GMAC_RXW1_ADDRMATCH (0x3u << 25) |
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/** Specific Address Register match found */ |
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#define GMAC_RXW1_ADDRFOUND (0x1u << 27) |
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/** Unicast hash match */ |
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#define GMAC_RXW1_UNIHASHMATCH (0x1u << 29) |
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/** Multicast hash match */ |
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#define GMAC_RXW1_MULTIHASHMATCH (0x1u << 30) |
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/** Global all ones broadcast address detected */ |
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#define GMAC_RXW1_BROADCASTDETECTED (0x1u << 31) |
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/* |
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* Transmit buffer descriptor bit field definitions |
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*/ |
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/** Transmit buffer length */ |
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#define GMAC_TXW1_LEN (0x3FFFu << 0) |
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/** Last buffer in the current frame */ |
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#define GMAC_TXW1_LASTBUFFER (0x1u << 15) |
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/** No CRC */ |
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#define GMAC_TXW1_NOCRC (0x1u << 16) |
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/** Transmit IP/TCP/UDP checksum generation offload errors */ |
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#define GMAC_TXW1_CHKSUMERR (0x7u << 20) |
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/** Late collision, transmit error detected */ |
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#define GMAC_TXW1_LATECOLERR (0x1u << 26) |
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/** Transmit frame corruption due to AHB error */ |
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#define GMAC_TXW1_TRANSERR (0x1u << 27) |
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/** Retry limit exceeded, transmit error detected */ |
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#define GMAC_TXW1_RETRYEXC (0x1u << 29) |
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/** Last descriptor in Transmit Descriptor list */ |
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#define GMAC_TXW1_WRAP (0x1u << 30) |
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/** Buffer used, must be 0 for the GMAC to read data to the transmit buffer */ |
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#define GMAC_TXW1_USED (0x1u << 31) |
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/* |
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* Interrupt Status/Enable/Disable/Mask register bit field definitions |
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*/ |
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#define GMAC_INT_RX_ERR_BITS \ |
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(GMAC_IER_RXUBR | GMAC_IER_ROVR) |
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#define GMAC_INT_TX_ERR_BITS \ |
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(GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC) |
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#define GMAC_INT_EN_FLAGS \ |
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(GMAC_IER_RCOMP | GMAC_INT_RX_ERR_BITS | \ |
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GMAC_IER_TCOMP | GMAC_INT_TX_ERR_BITS | GMAC_IER_HRESP) |
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#define GMAC_INTPQ_RX_ERR_BITS \ |
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(GMAC_IERPQ_RXUBR | GMAC_IERPQ_ROVR) |
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#define GMAC_INTPQ_TX_ERR_BITS \ |
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(GMAC_IERPQ_RLEX | GMAC_IERPQ_TFC) |
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#define GMAC_INTPQ_EN_FLAGS \ |
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(GMAC_IERPQ_RCOMP | GMAC_INTPQ_RX_ERR_BITS | \ |
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GMAC_IERPQ_TCOMP | GMAC_INTPQ_TX_ERR_BITS | GMAC_IERPQ_HRESP) |
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/** GMAC Priority Queues DMA flags */ |
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#if GMAC_PRIORITY_QUEUE_NUM >= 1 |
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/* 4 kB Receiver Packet Buffer Memory Size */ |
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/* 4 kB Transmitter Packet Buffer Memory Size */ |
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/* Transmitter Checksum Generation Offload Enable */ |
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#define GMAC_DMA_QUEUE_FLAGS \ |
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(GMAC_DCFGR_RXBMS_FULL | GMAC_DCFGR_TXPBMS | \ |
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GMAC_DCFGR_TXCOEN) |
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#else |
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#define GMAC_DMA_QUEUE_FLAGS (0) |
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#endif |
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/** List of GMAC queues */ |
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enum queue_idx { |
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GMAC_QUE_0, /** Main queue */ |
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GMAC_QUE_1, /** Priority queue 1 */ |
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GMAC_QUE_2, /** Priority queue 2 */ |
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GMAC_QUE_3, /** Priority queue 3 */ |
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GMAC_QUE_4, /** Priority queue 4 */ |
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GMAC_QUE_5, /** Priority queue 5 */ |
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}; |
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#if (DT_INST_PROP(0, max_frame_size) == 1518) |
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/* Maximum frame length is 1518 bytes */ |
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#define GMAC_MAX_FRAME_SIZE 0 |
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#elif (DT_INST_PROP(0, max_frame_size) == 1536) |
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/* Enable Max Frame Size of 1536 */ |
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#define GMAC_MAX_FRAME_SIZE GMAC_NCFGR_MAXFS |
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#elif (DT_INST_PROP(0, max_frame_size) == 10240) |
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/* Jumbo Frame Enable */ |
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#define GMAC_MAX_FRAME_SIZE GMAC_NCFGR_JFRAME |
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#else |
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#error "GMAC_MAX_FRAME_SIZE is invalid, fix it at device tree." |
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#endif |
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/** Minimal ring buffer implementation */ |
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struct ring_buffer { |
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uint32_t *buf; |
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uint16_t len; |
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uint16_t head; |
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uint16_t tail; |
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}; |
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/** Receive/transmit buffer descriptor */ |
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struct gmac_desc { |
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uint32_t w0; |
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uint32_t w1; |
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}; |
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/** Ring list of receive/transmit buffer descriptors */ |
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struct gmac_desc_list { |
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struct gmac_desc *buf; |
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uint16_t len; |
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uint16_t head; |
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uint16_t tail; |
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}; |
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/** GMAC Queue data */ |
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struct gmac_queue { |
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struct gmac_desc_list rx_desc_list; |
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struct gmac_desc_list tx_desc_list; |
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#if GMAC_MULTIPLE_TX_PACKETS == 1 |
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struct k_sem tx_desc_sem; |
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#else |
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struct k_sem tx_sem; |
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#endif |
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struct net_buf **rx_frag_list; |
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#if GMAC_MULTIPLE_TX_PACKETS == 1 |
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struct ring_buffer tx_frag_list; |
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#if defined(CONFIG_PTP_CLOCK_SAM_GMAC) |
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struct ring_buffer tx_frames; |
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#endif |
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#endif |
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/** Number of RX frames dropped by the driver */ |
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volatile uint32_t err_rx_frames_dropped; |
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/** Number of times receive queue was flushed */ |
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volatile uint32_t err_rx_flushed_count; |
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/** Number of times transmit queue was flushed */ |
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volatile uint32_t err_tx_flushed_count; |
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enum queue_idx que_idx; |
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}; |
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/* Device constant configuration parameters */ |
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struct eth_sam_dev_cfg { |
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Gmac *regs; |
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#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM |
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const struct atmel_sam_pmc_config clock_cfg; |
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#endif |
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const struct pinctrl_dev_config *pcfg; |
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void (*config_func)(void); |
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const struct device *phy_dev; |
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}; |
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/* Device run time data */ |
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struct eth_sam_dev_data { |
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struct net_if *iface; |
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#if defined(CONFIG_PTP_CLOCK_SAM_GMAC) |
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const struct device *ptp_clock; |
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#endif |
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uint8_t mac_addr[6]; |
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bool link_up; |
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struct gmac_queue queue_list[GMAC_QUEUE_NUM]; |
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}; |
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#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_SAM_GMAC_PRIV_H_ */
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