Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
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/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#define USE_NON_SECURE_ADDRESS_MAP 1
#include <nordic/nrf54l15_cpuapp.dtsi>
#include "nrf54l_05_10_15_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54l15dk_nrf54l15-cpuapp";
model = "Nordic nRF54L15 DK nRF54L15 Application MCU";
chosen {
zephyr,code-partition = &slot0_ns_partition;
zephyr,sram = &sram0_ns;
zephyr,entropy = &psa_rng;
};
/delete-node/ rng;
psa_rng: psa-rng {
status = "okay";
};
};
/ {
/*
* Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
* - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
* - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
*
* nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
* the FLPR MCU.
* This static layout needs to be the same with the upstream TF-M layout in the
* header flash_layout.h of the relevant platform. Any updates in the layout
* needs to happen both in the flash_layout.h and in this file at the same time.
*/
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram0_s: image_s@20000000 {
/* Secure image memory */
reg = <0x20000000 DT_SIZE_K(80)>;
};
sram0_ns: image_ns@20014000 {
/* Non-Secure image memory */
reg = <0x20014000 DT_SIZE_K(80)>;
};
};
};
&uart30 {
/* Disable so that TF-M can use this UART */
status = "disabled";
current-speed = <115200>;
pinctrl-0 = <&uart30_default>;
pinctrl-1 = <&uart30_sleep>;
pinctrl-names = "default", "sleep";
};
/* Include default memory partition configuration file */
#include <nordic/nrf54l15_ns_partition.dtsi>