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82 lines
1.9 KiB
82 lines
1.9 KiB
/* Copyright 2023 The ChromiumOS Authors |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/device.h> |
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#define DT_DRV_COMPAT mediatek_adsp_intc |
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struct intc_mtk_cfg { |
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uint32_t xtensa_irq; |
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uint32_t irq_mask; |
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uint32_t sw_isr_off; |
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volatile uint32_t *enable_reg; |
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volatile uint32_t *status_reg; |
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}; |
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bool intc_mtk_adsp_get_enable(const struct device *dev, int irq) |
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{ |
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const struct intc_mtk_cfg *cfg = dev->config; |
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return (*cfg->enable_reg | (BIT(irq) & cfg->irq_mask)) != 0; |
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} |
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void intc_mtk_adsp_set_enable(const struct device *dev, int irq, bool val) |
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{ |
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const struct intc_mtk_cfg *cfg = dev->config; |
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irq_enable(cfg->xtensa_irq); |
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if ((BIT(irq) & cfg->irq_mask) != 0) { |
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if (val) { |
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*cfg->enable_reg |= BIT(irq); |
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} else { |
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*cfg->enable_reg &= ~BIT(irq); |
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} |
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} |
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} |
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static void intc_isr(const void *arg) |
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{ |
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const struct intc_mtk_cfg *cfg = ((struct device *)arg)->config; |
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uint32_t irqs = *cfg->status_reg & cfg->irq_mask; |
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while (irqs != 0) { |
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uint32_t irq = find_msb_set(irqs) - 1; |
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uint32_t off = cfg->sw_isr_off + irq; |
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_sw_isr_table[off].isr(_sw_isr_table[off].arg); |
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irqs &= ~BIT(irq); |
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} |
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} |
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static void dev_init(const struct device *dev) |
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{ |
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const struct intc_mtk_cfg *cfg = dev->config; |
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*cfg->enable_reg = 0; |
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irq_enable(cfg->xtensa_irq); |
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} |
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#define DEV_INIT(N) \ |
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IRQ_CONNECT(DT_INST_IRQN(N), 0, intc_isr, DEVICE_DT_INST_GET(N), 0); \ |
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dev_init(DEVICE_DT_INST_GET(N)); |
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static int intc_init(void) |
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{ |
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DT_INST_FOREACH_STATUS_OKAY(DEV_INIT); |
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return 0; |
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} |
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SYS_INIT(intc_init, PRE_KERNEL_1, 0); |
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#define DEF_DEV(N) \ |
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static const struct intc_mtk_cfg dev_cfg##N = { \ |
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.xtensa_irq = DT_INST_IRQN(N), \ |
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.irq_mask = DT_INST_PROP(N, mask), \ |
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.sw_isr_off = (N + 1) * 32, \ |
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.enable_reg = (void *)DT_INST_REG_ADDR(N), \ |
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.status_reg = (void *)DT_INST_PROP(N, status_reg) }; \ |
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DEVICE_DT_INST_DEFINE(N, NULL, NULL, NULL, &dev_cfg##N, PRE_KERNEL_1, 0, NULL); |
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DT_INST_FOREACH_STATUS_OKAY(DEF_DEV);
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