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80 lines
2.6 KiB
80 lines
2.6 KiB
/* |
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef __SOC_H__ |
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#define __SOC_H__ |
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#include <soc/syscon_reg.h> |
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#include <soc/system_reg.h> |
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#include <soc/dport_access.h> |
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#include <soc/rtc_cntl_reg.h> |
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#include <soc/soc_caps.h> |
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#include <esp32s2/rom/ets_sys.h> |
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#include <esp32s2/rom/spi_flash.h> |
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#include <esp32s2/rom/cache.h> |
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#include <esp_private/esp_clk.h> |
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#include <esp_rom_sys.h> |
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#include <zephyr/types.h> |
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#include <stdbool.h> |
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#include <zephyr/arch/xtensa/arch.h> |
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#include <stdlib.h> |
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void __esp_platform_mcuboot_start(void); |
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void __esp_platform_app_start(void); |
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static inline uint32_t esp_core_id(void) |
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{ |
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return 0; |
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} |
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extern void esp_rom_uart_attach(void); |
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extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no); |
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extern int esp_rom_uart_tx_one_char(uint8_t chr); |
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extern int esp_rom_uart_rx_one_char(uint8_t *chr); |
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extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index, bool inverted); |
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extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index, |
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bool out_invrted, bool out_enabled_inverted); |
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/* cache related rom functions */ |
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extern uint32_t esp_rom_Cache_Disable_ICache(void); |
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extern uint32_t esp_rom_Cache_Disable_DCache(void); |
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extern void esp_rom_Cache_Allocate_SRAM(cache_layout_t sram0_layout, cache_layout_t sram1_layout, |
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cache_layout_t sram2_layout, cache_layout_t sram3_layout); |
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extern uint32_t esp_rom_Cache_Suspend_ICache(void); |
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extern void esp_rom_Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, |
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cache_line_size_t cache_line_size); |
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extern void esp_rom_Cache_Invalidate_ICache_All(void); |
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extern void esp_rom_Cache_Resume_ICache(uint32_t autoload); |
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extern int esp_rom_Cache_Invalidate_Addr(uint32_t addr, uint32_t size); |
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/* data-cache related rom functions */ |
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extern void esp_rom_Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, |
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cache_line_size_t cache_line_size); |
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extern void esp_rom_Cache_Invalidate_DCache_All(void); |
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extern void esp_rom_Cache_Enable_DCache(uint32_t autoload); |
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extern void esp_rom_Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, |
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cache_line_size_t cache_line_size); |
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extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, |
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uint32_t psize, uint32_t num, uint32_t fixed); |
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/* ROM information related to SPI Flash chip timing and device */ |
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extern esp_rom_spiflash_chip_t g_rom_flashchip; |
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extern uint8_t g_rom_spiflash_dummy_len_plus[]; |
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extern uint32_t esp_rom_g_ticks_per_us_pro; |
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/* cache initialization functions */ |
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void esp_config_instruction_cache_mode(void); |
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void esp_config_data_cache_mode(void); |
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#endif /* __SOC_H__ */
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