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326 lines
10 KiB
326 lines
10 KiB
/* |
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <soc.h> |
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#include <hal/mmu_hal.h> |
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#include <hal/mmu_types.h> |
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#include <hal/cache_types.h> |
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#include <hal/cache_ll.h> |
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#include <hal/cache_hal.h> |
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#include <rom/cache.h> |
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#include <esp_rom_sys.h> |
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#include <esp_err.h> |
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#include <esp_app_format.h> |
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#include <zephyr/storage/flash_map.h> |
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#include <esp_rom_uart.h> |
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#include <esp_flash.h> |
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#include <esp_log.h> |
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#include <bootloader_clock.h> |
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#include <bootloader_common.h> |
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#include <esp_cpu.h> |
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#include <zephyr/linker/linker-defs.h> |
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#include <kernel_internal.h> |
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#if CONFIG_SOC_SERIES_ESP32C6 |
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#include <soc/hp_apm_reg.h> |
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#include <soc/lp_apm_reg.h> |
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#include <soc/lp_apm0_reg.h> |
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#include <soc/pcr_reg.h> |
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#endif /* CONFIG_SOC_SERIES_ESP32C6 */ |
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#include <esp_flash_internal.h> |
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#include <bootloader_flash.h> |
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#include <bootloader_flash_priv.h> |
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#include <hal/efuse_ll.h> |
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#include <hal/efuse_hal.h> |
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#include <hal/wdt_hal.h> |
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#include <soc/chip_revision.h> |
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#include <soc/rtc.h> |
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#ifndef CONFIG_SOC_SERIES_ESP32 |
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#include <soc/assist_debug_reg.h> |
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#include <soc/system_reg.h> |
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#endif |
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#include "hw_init.h" |
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#include "soc_init.h" |
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#include "soc_random.h" |
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#if defined(CONFIG_SOC_ESP32S3_APPCPU) || defined(CONFIG_SOC_ESP32_APPCPU) |
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#error "APPCPU does not need this file!" |
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#endif |
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#define TAG "boot" |
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#define CHECKSUM_ALIGN 16 |
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#define IS_PADD(addr) (addr == 0) |
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#define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) |
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#define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) |
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#define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) |
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#define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) |
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#ifdef SOC_RTC_MEM_SUPPORTED |
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#define IS_RTC(addr) (addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH) |
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#else |
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#define IS_RTC(addr) 0 |
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#endif |
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#define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr)) |
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#define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr)) |
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#define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \ |
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&& !IS_IRAM(addr) && !IS_DRAM(addr) && !IS_PADD(addr) && !IS_RTC(addr)) |
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#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) |
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#if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU) |
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#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_partition) |
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#else |
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#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_appcpu_partition) |
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#endif |
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void __start(void); |
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static HDR_ATTR void (*_entry_point)(void) = &__start; |
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esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr; |
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extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; |
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extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; |
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#ifndef CONFIG_MCUBOOT |
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extern uint32_t _libc_heap_size; |
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static uint32_t libc_heap_size = (uint32_t)&_libc_heap_size; |
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static struct rom_segments map = { |
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.irom_map_addr = (uint32_t)&_image_irom_vaddr, |
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.irom_flash_offset = PART_OFFSET + (uint32_t)&_image_irom_start, |
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.irom_size = (uint32_t)&_image_irom_size, |
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.drom_map_addr = ((uint32_t)&_image_drom_vaddr), |
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.drom_flash_offset = PART_OFFSET + (uint32_t)&_image_drom_start, |
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.drom_size = (uint32_t)&_image_drom_size, |
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}; |
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void map_rom_segments(int core, struct rom_segments *map) |
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{ |
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uint32_t app_irom_vaddr_align = map->irom_map_addr & MMU_FLASH_MASK; |
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uint32_t app_irom_start_align = map->irom_flash_offset & MMU_FLASH_MASK; |
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uint32_t app_drom_vaddr_align = map->drom_map_addr & MMU_FLASH_MASK; |
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uint32_t app_drom_start_align = map->drom_flash_offset & MMU_FLASH_MASK; |
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/* Traverse segments to fix flash offset changes due to post-build processing */ |
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#ifndef CONFIG_BOOTLOADER_MCUBOOT |
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esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr; |
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size_t offset = FIXED_PARTITION_OFFSET(boot_partition); |
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bool checksum = false; |
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unsigned int segments = 0; |
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unsigned int ram_segments = 0; |
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offset += sizeof(esp_image_header_t); |
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while (segments++ < 16) { |
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if (esp_rom_flash_read(offset, &segment_hdr, |
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sizeof(esp_image_segment_header_t), true) != 0) { |
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ESP_EARLY_LOGE(TAG, "Failed to read segment header at %x", offset); |
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abort(); |
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} |
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/* TODO: Find better end-of-segment detection */ |
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if (IS_NONE(segment_hdr.load_addr)) { |
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/* Total segment count = (segments - 1) */ |
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break; |
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} |
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ESP_EARLY_LOGI(TAG, "%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)", |
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IS_NONE(segment_hdr.load_addr) ? "???" : |
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IS_MMAP(segment_hdr.load_addr) ? |
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IS_IROM(segment_hdr.load_addr) ? "IMAP" : "DMAP" : |
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IS_DRAM(segment_hdr.load_addr) ? "DRAM" : |
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IS_RTC(segment_hdr.load_addr) ? "RTC" : "IRAM", |
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offset + sizeof(esp_image_segment_header_t), |
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segment_hdr.load_addr, segment_hdr.data_len, segment_hdr.data_len); |
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/* Fix drom and irom produced be the linker, as it could |
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* be invalidated by the elf2image and flash load offset |
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*/ |
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if (segment_hdr.load_addr == map->drom_map_addr) { |
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map->drom_flash_offset = offset + sizeof(esp_image_segment_header_t); |
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app_drom_start_align = map->drom_flash_offset & MMU_FLASH_MASK; |
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} |
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if (segment_hdr.load_addr == map->irom_map_addr) { |
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map->irom_flash_offset = offset + sizeof(esp_image_segment_header_t); |
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app_irom_start_align = map->irom_flash_offset & MMU_FLASH_MASK; |
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} |
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if (IS_SRAM(segment_hdr.load_addr) || IS_RTC(segment_hdr.load_addr)) { |
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ram_segments++; |
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} |
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offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len; |
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if (ram_segments == bootloader_image_hdr.segment_count && !checksum) { |
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offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1; |
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checksum = true; |
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} |
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} |
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if (segments == 0 || segments == 16) { |
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ESP_EARLY_LOGE(TAG, "Error parsing segments"); |
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abort(); |
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} |
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ESP_EARLY_LOGI(TAG, "Image with %d segments", segments - 1); |
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#endif /* !CONFIG_BOOTLOADER_MCUBOOT */ |
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#if CONFIG_SOC_SERIES_ESP32 |
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Cache_Read_Disable(core); |
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Cache_Flush(core); |
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#else |
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cache_hal_disable(CACHE_TYPE_ALL); |
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#endif /* CONFIG_SOC_SERIES_ESP32 */ |
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/* Clear the MMU entries that are already set up, |
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* so the new app only has the mappings it creates. |
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*/ |
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if (core == 0) { |
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mmu_hal_unmap_all(); |
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} |
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#if CONFIG_SOC_SERIES_ESP32 |
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int rc = 0; |
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uint32_t drom_page_count = |
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(map->drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; |
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rc |= cache_flash_mmu_set(core, 0, app_drom_vaddr_align, app_drom_start_align, 64, |
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drom_page_count); |
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uint32_t irom_page_count = |
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(map->irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; |
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rc |= cache_flash_mmu_set(core, 0, app_irom_vaddr_align, app_irom_start_align, 64, |
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irom_page_count); |
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if (rc != 0) { |
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ESP_EARLY_LOGE(TAG, "Failed to setup flash cache (e=0x%X). Aborting!", rc); |
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abort(); |
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} |
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#else |
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uint32_t actual_mapped_len = 0; |
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mmu_hal_map_region(core, MMU_TARGET_FLASH0, app_drom_vaddr_align, app_drom_start_align, |
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map->drom_size, &actual_mapped_len); |
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mmu_hal_map_region(core, MMU_TARGET_FLASH0, app_irom_vaddr_align, app_irom_start_align, |
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map->irom_size, &actual_mapped_len); |
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#endif /* CONFIG_SOC_SERIES_ESP32 */ |
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/* ----------------------Enable corresponding buses---------------- */ |
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cache_bus_mask_t bus_mask; |
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bus_mask = cache_ll_l1_get_bus(core, app_drom_vaddr_align, map->drom_size); |
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cache_ll_l1_enable_bus(core, bus_mask); |
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bus_mask = cache_ll_l1_get_bus(core, app_irom_vaddr_align, map->irom_size); |
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cache_ll_l1_enable_bus(core, bus_mask); |
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#if CONFIG_MP_MAX_NUM_CPUS > 1 |
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bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_align, map->drom_size); |
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cache_ll_l1_enable_bus(1, bus_mask); |
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bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_align, map->irom_size); |
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cache_ll_l1_enable_bus(1, bus_mask); |
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#endif |
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/* ----------------------Enable Cache---------------- */ |
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#if CONFIG_SOC_SERIES_ESP32 |
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/* Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) */ |
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Cache_Read_Enable(core); |
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#else |
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cache_hal_enable(CACHE_TYPE_ALL); |
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#endif /* CONFIG_SOC_SERIES_ESP32 */ |
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#if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32S2) |
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/* Configure the Cache MMU size for instruction and rodata in flash. */ |
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uint32_t cache_mmu_irom_size = |
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((map->irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) * |
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sizeof(uint32_t); |
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/* Split the cache usage by the segment sizes */ |
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Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); |
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#endif |
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} |
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#endif /* !CONFIG_MCUBOOT */ |
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void __start(void) |
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{ |
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#ifdef CONFIG_RISCV_GP |
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__asm__ __volatile__("la t0, _esp_vector_table\n" |
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"csrw mtvec, t0\n"); |
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/* Disable normal interrupts. */ |
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csr_read_clear(mstatus, MSTATUS_MIE); |
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/* Configure the global pointer register |
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* (This should be the first thing startup does, as any other piece of code could be |
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* relaxed by the linker to access something relative to __global_pointer$) |
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*/ |
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__asm__ __volatile__(".option push\n" |
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".option norelax\n" |
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"la gp, __global_pointer$\n" |
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".option pop"); |
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z_bss_zero(); |
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#else /* xtensa */ |
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extern uint32_t _init_start; |
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/* Move the exception vector table to IRAM. */ |
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__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); |
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z_bss_zero(); |
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__asm__ __volatile__("" : : "g"(&__bss_start) : "memory"); |
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/* Disable normal interrupts. */ |
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__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); |
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/* Initialize the architecture CPU pointer. Some of the |
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* initialization code wants a valid arch_current_thread() before |
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* arch_kernel_init() is invoked. |
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*/ |
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__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); |
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#endif /* CONFIG_RISCV_GP */ |
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/* Initialize hardware only during 1st boot */ |
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#if defined(CONFIG_MCUBOOT) || defined(CONFIG_ESP_SIMPLE_BOOT) |
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if (hardware_init()) { |
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ESP_EARLY_LOGE(TAG, "HW init failed, aborting"); |
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abort(); |
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} |
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#endif |
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#if defined(CONFIG_ESP_SIMPLE_BOOT) || defined(CONFIG_BOOTLOADER_MCUBOOT) |
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map_rom_segments(0, &map); |
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/* Show map segments continue using same log format as during MCUboot phase */ |
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ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "IROM", |
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map.irom_flash_offset, map.irom_map_addr, map.irom_size, map.irom_size); |
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ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "DROM", |
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map.drom_flash_offset, map.drom_map_addr, map.drom_size, map.drom_size); |
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esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); |
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/* Disable RNG entropy source as it was already used */ |
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soc_random_disable(); |
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/* Disable glitch detection as it can be falsely triggered by EMI interference */ |
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ana_clock_glitch_reset_config(false); |
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ESP_EARLY_LOGI(TAG, "libc heap size %d kB.", libc_heap_size / 1024); |
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__esp_platform_app_start(); |
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#endif /* CONFIG_ESP_SIMPLE_BOOT || CONFIG_BOOTLOADER_MCUBOOT */ |
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#if defined(CONFIG_MCUBOOT) |
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__esp_platform_mcuboot_start(); |
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#endif |
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}
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