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364 lines
12 KiB
364 lines
12 KiB
.. _nucleo_l552ze_q_board: |
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ST Nucleo L552ZE Q |
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################## |
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Overview |
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The Nucleo L552ZE Q board, featuring an ARM Cortex-M33 based STM32L552ZE MCU, |
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provides an affordable and flexible way for users to try out new concepts and |
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build prototypes by choosing from the various combinations of performance and |
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power consumption features. Here are some highlights of the Nucleo L552ZE Q |
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board: |
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- STM32L552ZE microcontroller in LQFP144 package |
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- Two types of extension resources: |
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- Arduino Uno V3 connectivity |
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- ST morpho extension pin headers for full access to all STM32 I/Os |
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- On-board ST-LINK/V2-1 debugger/programmer with SWD connector |
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- Flexible board power supply: |
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- USB VBUS or external source(3.3V, 5V, 7 - 12V) |
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- ST-Link |
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- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) |
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- Two push-buttons: USER and RESET |
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- External or internal SMPS to generate Vcore logic supply |
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- USB OTG full speed or device only |
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.. image:: img/nucleo_l552ze_q.jpg |
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:align: center |
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:alt: Nucleo L552ZE Q |
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More information about the board can be found at the `Nucleo L552ZE Q website`_. |
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Hardware |
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The STM32L552xx devices are an ultra-low-power microcontrollers family (STM32L5 |
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Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. |
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They operate at a frequency of up to 110 MHz. |
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- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode) |
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- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. |
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- Performance benchmark: |
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- 1.5 DMPIS/MHz (Drystone 2.1) |
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- 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ) |
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- Security |
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- Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals |
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- Flexible life cycle scheme with RDP (readout protection) |
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- Root of trust thanks to unique boot entry and hide protection area (HDP) |
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- Secure Firmware Installation thanks to embedded Root Secure Services |
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- Secure Firmware Update support with TF-M |
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- HASH hardware accelerator |
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- Active tamper and protection temperature, voltage and frequency attacks |
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- True Random Number Generator NIST SP800-90B compliant |
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- 96-bit unique ID |
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- 512-byte One-Time Programmable for user data |
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- Clock management: |
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- 4 to 48 MHz crystal oscillator |
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- 32 kHz crystal oscillator for RTC (LSE) |
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- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) |
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- Internal low-power 32 kHz RC ( |plusminus| 5%) |
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- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by |
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LSE (better than |plusminus| 0.25 % accuracy) |
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- 3 PLLs for system clock, USB, audio, ADC |
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- Power management |
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- Embedded regulator (LDO) with three configurable range output to supply the digital circuitry |
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- Embedded SMPS step-down converter |
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- External SMPS support |
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- RTC with HW calendar, alarms and calibration |
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- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V |
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- Up to 22 capacitive sensing channels: support touchkey, linear and rotary touch sensors |
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- Up to 16 timers and 2 watchdogs |
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- 2x 16-bit advanced motor-control |
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- 2x 32-bit and 5x 16-bit general purpose |
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- 2x 16-bit basic |
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- 3x low-power 16-bit timers (available in Stop mode) |
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- 2x watchdogs |
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- 2x SysTick timer |
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- Memories |
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- Up to 512 MB Flash, 2 banks read-while-write |
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- 512 KB of SRAM including 64 KB with hardware parity check |
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- External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories |
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- OCTOSPI memory interface |
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- Rich analog peripherals (independent supply) |
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- 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS |
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- 2x 12-bit DAC, low-power sample and hold |
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- 2x operational amplifiers with built-in PGA |
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- 2x ultra-low-power comparators |
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- 4x digital filters for sigma delta modulator |
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- 19x communication interfaces |
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- USB Type-C / USB power delivery controller |
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- 2.0 full-speed crystal less solution, LPM and BCD |
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- 2x SAIs (serial audio interface) |
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- 4x I2C FM+(1 Mbit/s), SMBus/PMBus |
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- 6x USARTs (ISO 7816, LIN, IrDA, modem) |
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- 3x SPIs (7x SPIs with USART and OCTOSPI in SPI mode) |
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- 1xFDCAN |
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- 1xSDMMC interface |
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- 2x 14 channel DMA controllers |
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- CRC calculation unit |
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- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| |
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More information about STM32L552ZE can be found here: |
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- `STM32L552ZE on www.st.com`_ |
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- `STM32L552 reference manual`_ |
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Supported Features |
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================== |
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The Zephyr nucleo_l552ze_q board configuration supports the following |
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hardware features: |
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+-----------+------------+-------------------------------------+ |
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| Interface | Controller | Driver/Component | |
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+===========+============+=====================================+ |
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| ADC | on-chip | ADC Controller | |
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+-----------+------------+-------------------------------------+ |
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| CLOCK | on-chip | reset and clock control | |
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+-----------+------------+-------------------------------------+ |
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| DAC | on-chip | DAC Controller | |
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+-----------+------------+-------------------------------------+ |
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| DMA | on-chip | Direct Memory Access | |
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+-----------+------------+-------------------------------------+ |
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| GPIO | on-chip | gpio | |
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+-----------+------------+-------------------------------------+ |
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| I2C | on-chip | i2c | |
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+-----------+------------+-------------------------------------+ |
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| NVIC | on-chip | nested vector interrupt controller | |
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+-----------+------------+-------------------------------------+ |
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| PINMUX | on-chip | pinmux | |
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+-----------+------------+-------------------------------------+ |
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| RNG | on-chip | entropy | |
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+-----------+------------+-------------------------------------+ |
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| SPI | on-chip | spi | |
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+-----------+------------+-------------------------------------+ |
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| TrustZone | on-chip | Trusted Firmware-M | |
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+-----------+------------+-------------------------------------+ |
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| UART | on-chip | serial port-polling; | |
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| | | serial port-interrupt | |
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+-----------+------------+-------------------------------------+ |
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| die-temp | on-chip | die temperature sensor | |
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+-----------+------------+-------------------------------------+ |
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The default configuration can be found in the defconfig and dts files: |
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- Common: |
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- :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi` |
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- Secure target: |
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- :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig` |
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- :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts` |
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- Non-Secure target: |
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- :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig` |
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- :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts` |
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Zephyr board options |
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==================== |
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The STM32L552e is an SoC with Cortex-M33 architecture. Zephyr provides support |
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for building for both Secure and Non-Secure firmware. |
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The BOARD options are summarized below: |
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+--------------------------------+-------------------------------------------+ |
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| BOARD | Description | |
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+================================+===========================================+ |
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| nucleo_l552ze_q | For building Trust Zone Disabled firmware | |
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+--------------------------------+-------------------------------------------+ |
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| nucleo_l552ze_q/stm32l552xx/ns | For building Non-Secure firmware | |
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+--------------------------------+-------------------------------------------+ |
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Here are the instructions to build Zephyr with a non-secure configuration, |
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using :ref:`tfm_ipc` sample: |
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.. code-block:: console |
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$ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/ |
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Once done, before flashing, you need to first run a generated script that |
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will set platform option bytes config and erase platform (among others, |
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option bit TZEN will be set). |
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.. code-block:: bash |
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$ ./build/tfm/api_ns/regression.sh |
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$ west flash |
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Please note that, after having run a TFM sample on the board, you will need to |
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run ``./build/tfm/api_ns/regression.sh`` once more to clean up the board from secure |
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options and get back the platform back to a "normal" state and be able to run |
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usual, non-TFM, binaries. |
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Also note that, even then, TZEN will remain set, and you will need to use |
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STM32CubeProgrammer_ to disable it fully, if required. |
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Connections and IOs |
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=================== |
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Nucleo L552ZE Q Board has 8 GPIO controllers. These controllers are responsible for pin muxing, |
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input/output, pull-up, etc. |
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Available pins: |
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--------------- |
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.. image:: img/nucleo_l552ze_q_zio_left_2020_2_11.jpg |
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:align: center |
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:alt: Nucleo L552ZE Q Zio left connector |
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.. image:: img/nucleo_l552ze_q_zio_right_2020_2_11.jpg |
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:align: center |
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:alt: Nucleo L552ZE Q Zio right connector |
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For more details please refer to `STM32 Nucleo-144 board User Manual`_. |
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Default Zephyr Peripheral Mapping: |
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---------------------------------- |
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- UART_1_TX : PA9 |
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- UART_1_RX : PA10 |
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- UART_2_TX : PA2 |
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- UART_2_RX : PA3 |
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- UART_3_TX : PD8 |
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- UART_3_RX : PD9 |
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- I2C_1_SCL : PB6 |
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- I2C_1_SDA : PB7 |
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- SPI_1_NSS : PA4 |
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- SPI_1_SCK : PA5 |
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- SPI_1_MISO : PA6 |
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- SPI_1_MOSI : PA7 |
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- SPI_2_NSS : PB12 |
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- SPI_2_SCK : PB13 |
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- SPI_2_MISO : PB14 |
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- SPI_2_MOSI : PB15 |
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- SPI_3_NSS : PB12 |
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- SPI_3_SCK : PC10 |
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- SPI_3_MISO : PC11 |
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- SPI_3_MOSI : PC12 |
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- PWM_2_CH1 : PA0 |
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- USER_PB : PC13 |
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- LD2 : PB7 |
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- DAC1 : PA4 |
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- ADC1 : PC0 |
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System Clock |
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------------ |
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Nucleo L552ZE Q System Clock could be driven by internal or external oscillator, |
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as well as main PLL clock. By default System clock is driven by PLL clock at |
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110MHz, driven by 4MHz medium speed internal oscillator. |
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Serial Port |
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----------- |
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Nucleo L552ZE Q board has 6 U(S)ARTs. The Zephyr console output is assigned to |
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UART2. Default settings are 115200 8N1. |
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Programming and Debugging |
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************************* |
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Nucleo L552ZE Q board includes an ST-LINK/V2-1 embedded debug tool interface. |
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Applications for the ``nucleo_l552ze_q`` board configuration can be built and |
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flashed in the usual way (see :ref:`build_an_application` and |
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:ref:`application_run` for more details). |
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Flashing |
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======== |
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The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, |
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so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required. |
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Alternatively, OpenOCD or pyOCD can also be used to flash the board using |
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the ``--runner`` (or ``-r``) option: |
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.. code-block:: console |
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$ west flash --runner openocd |
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$ west flash --runner pyocd |
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Support can be enabled for pyOCD by adding "pack" support with the |
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following pyOCD commands: |
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.. code-block:: console |
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$ pyocd pack --update |
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$ pyocd pack --install stm32l552ze |
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Flashing an application to Nucleo L552ZE Q |
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------------------------------------------ |
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Connect the Nucleo L552ZE Q to your host computer using the USB port. |
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Then build and flash an application. Here is an example for the |
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:ref:`hello_world` application. |
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Run a serial host program to connect with your Nucleo board: |
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.. code-block:: console |
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$ minicom -D /dev/ttyACM0 |
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Then build and flash the application. |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: nucleo_l552ze_q |
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:goals: build flash |
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You should see the following message on the console: |
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.. code-block:: console |
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Hello World! arm |
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Debugging |
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========= |
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You can debug an application in the usual way. Here is an example for the |
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:ref:`hello_world` application. |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: nucleo_l552ze_q |
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:maybe-skip-config: |
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:goals: debug |
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.. _Nucleo L552ZE Q website: |
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https://www.st.com/en/evaluation-tools/nucleo-l552ze-q.html |
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.. _STM32 Nucleo-144 board User Manual: |
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https://www.st.com/resource/en/user_manual/dm00615305.pdf |
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.. _STM32L552ZE on www.st.com: |
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https://www.st.com/en/microcontrollers/stm32l552ze.html |
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.. _STM32L552 reference manual: |
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https://www.st.com/resource/en/reference_manual/DM00346336.pdf |
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.. _STM32CubeProgrammer: |
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https://www.st.com/en/development-tools/stm32cubeprog.html
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