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334 lines
11 KiB
334 lines
11 KiB
.. _s32z2xxdc2: |
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NXP X-S32Z27X-DC (DC2) |
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###################### |
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Overview |
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******** |
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The X-S32Z27X-DC (DC2) board is based on the NXP S32Z2 Real-Time Processor, |
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which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores |
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each, with flexible split/lock configurations. |
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There is one Zephyr board per SoC/RTU: |
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- ``s32z2xxdc2/s32z270/rtu0``, for S32Z270/RTU0 |
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- ``s32z2xxdc2/s32z270/rtu1``, for S32Z270/RTU1. |
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Hardware |
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******** |
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Information about the hardware and design resources can be found at |
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`NXP S32Z2 Real-Time Processors website`_. |
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Supported Features |
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================== |
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The boards support the following hardware features: |
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+-----------+------------+-------------------------------------+ |
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| Interface | Controller | Driver/Component | |
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+===========+============+=====================================+ |
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| Arm GIC | on-chip | interrupt_controller | |
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+-----------+------------+-------------------------------------+ |
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| Arm Timer | on-chip | timer | |
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+-----------+------------+-------------------------------------+ |
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| LINFlexD | on-chip | serial | |
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+-----------+------------+-------------------------------------+ |
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| MRU | on-chip | mbox | |
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+-----------+------------+-------------------------------------+ |
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| NETC | on-chip | ethernet | |
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| | | | |
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| | | mdio | |
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+-----------+------------+-------------------------------------+ |
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| SIUL2 | on-chip | pinctrl | |
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| | | | |
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| | | gpio | |
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| | | | |
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| | | external interrupt controller | |
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+-----------+------------+-------------------------------------+ |
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| SPI | on-chip | spi | |
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+-----------+------------+-------------------------------------+ |
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| SWT | on-chip | watchdog | |
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+-----------+------------+-------------------------------------+ |
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| CANEXCEL | on-chip | can | |
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+-----------+------------+-------------------------------------+ |
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| FLEXCAN | on-chip | can | |
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+-----------+------------+-------------------------------------+ |
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| SAR_ADC | on-chip | adc | |
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+-----------+------------+-------------------------------------+ |
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| LPI2C | on-chip | i2c | |
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+-----------+------------+-------------------------------------+ |
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Other hardware features are not currently supported by the port. |
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Connections and IOs |
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=================== |
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The SoC's pads are grouped into ports and pins for consistency with GPIO driver |
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and the HAL drivers used by this Zephyr port. The following table summarizes |
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the mapping between pads and ports/pins. This must be taken into account when |
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using GPIO driver or configuring the pinmuxing for the device drivers. |
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+-------------------+-------------+ |
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| Pads | Port/Pins | |
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+===================+=============+ |
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| PAD_000 - PAD_015 | PA0 - PA15 | |
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+-------------------+-------------+ |
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| PAD_016 - PAD_030 | PB0 - PB14 | |
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+-------------------+-------------+ |
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| PAD_031 | PC15 | |
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+-------------------+-------------+ |
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| PAD_032 - PAD_047 | PD0 - PD15 | |
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+-------------------+-------------+ |
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| PAD_048 - PAD_063 | PE0 - PE15 | |
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+-------------------+-------------+ |
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| PAD_064 - PAD_079 | PF0 - PF15 | |
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+-------------------+-------------+ |
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| PAD_080 - PAD_091 | PG0 - PG11 | |
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+-------------------+-------------+ |
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| PAD_092 - PAD_095 | PH12 - PH15 | |
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+-------------------+-------------+ |
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| PAD_096 - PAD_111 | PI0 - PI15 | |
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+-------------------+-------------+ |
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| PAD_112 - PAD_127 | PJ0 - PJ15 | |
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+-------------------+-------------+ |
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| PAD_128 - PAD_143 | PK0 - PK15 | |
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+-------------------+-------------+ |
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| PAD_144 - PAD_145 | PL0 - PL1 | |
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+-------------------+-------------+ |
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| PAD_146 - PAD_159 | PM2 - PM15 | |
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+-------------------+-------------+ |
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| PAD_160 - PAD_169 | PN0 - PN9 | |
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+-------------------+-------------+ |
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| PAD_170 - PAD_173 | PO10 - PO13 | |
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+-------------------+-------------+ |
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This board does not include user LED's or switches, which are needed for some |
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of the samples such as :zephyr:code-sample:`blinky` or :zephyr:code-sample:`button`. |
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Follow the steps described in the sample description to enable support for this |
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board. |
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System Clock |
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============ |
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The Cortex-R52 cores are configured to run at 1 GHz. |
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Serial Port |
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=========== |
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The SoC has 12 LINFlexD instances that can be used in UART mode. The console can |
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be accessed by default on the USB micro-B connector J119. |
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Watchdog |
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======== |
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The watchdog driver only supports triggering an interrupt upon timer expiration. |
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Zephyr is currently running from SRAM on this board, thus system reset is not |
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supported. |
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Ethernet |
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======== |
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NETC driver supports to manage the Physical Station Interface (PSI0) and/or a |
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single Virtual SI (VSI). The rest of the VSI's shall be assigned to different |
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cores of the system. Refer to :zephyr:code-sample:`nxp_s32_netc` to learn how to |
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configure the Ethernet network controller. |
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Controller Area Network |
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======================= |
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CANEXCEL |
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-------- |
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CANEXCEL supports CAN Classic (CAN 2.0) and CAN FD modes. Remote transmission |
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request is not supported. |
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Note that this board does not currently come with CAN transceivers installed for |
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the CANEXCEL ports. To facilitate external traffic, you will need to add a CAN |
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transceiver. Any transceiver pin-compatible with CAN 2.0 and CAN FD protocols |
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can be used. |
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FlexCAN |
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------- |
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FlexCAN supports CAN Classic (CAN 2.0) and CAN FD modes. |
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ADC |
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=== |
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ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instance has |
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12-bit resolution. ADC channels are divided into 2 groups (precision and internal/standard). |
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.. note:: |
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All channels of an instance only run on 1 group channel at the same time. |
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Programming and Debugging |
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************************* |
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Applications for the ``s32z2xxdc2`` boards can be built in the usual way as |
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documented in :ref:`build_an_application`. |
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Currently is only possible to load and execute a Zephyr application binary on |
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this board from the core internal SRAM. |
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This board supports West runners for the following debug tools: |
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- :ref:`NXP S32 Debug Probe <nxp-s32-debug-probe>` (default) |
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- :ref:`Lauterbach TRACE32 <lauterbach-trace32-debug-host-tools>` |
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Follow the installation steps of the debug tool you plan to use before loading |
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your firmware. |
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Set-up the Board |
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================ |
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Connect the external debugger probe to the board's JTAG connector (``J134``) |
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and to the host computer via USB or Ethernet, as supported by the probe. |
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For visualizing the serial output, connect the board's USB/UART port (``J119``) to |
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the host computer and run your favorite terminal program to listen for output. |
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For example, using the cross-platform `pySerial miniterm`_ terminal: |
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.. code-block:: console |
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python -m serial.tools.miniterm <port> 115200 |
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Replace ``<port>`` with the port where the board can be found. For example, |
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under Linux, ``/dev/ttyUSB0``. |
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Debugging |
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========= |
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You can build and debug the :ref:`hello_world` sample for the board |
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``s32z2xxdc2/s32z270/rtu0`` with: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: s32z2xxdc2/s32z270/rtu0 |
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:goals: build debug |
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In case you are using a newer PCB revision, you have to use an adapted board |
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definition as the default PCB revision is B. For example, if using revision D: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: s32z2xxdc2@D/s32z270/rtu0 |
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:goals: build debug |
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:compact: |
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At this point you can do your normal debug session. Set breakpoints and then |
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:kbd:`c` to continue into the program. You should see the following message in |
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the terminal: |
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.. code-block:: console |
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Hello World! s32z2xxdc2 |
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To debug with Lauterbach TRACE32 softare run instead: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: s32z2xxdc2/s32z270/rtu0 |
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:goals: build debug -r trace32 |
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:compact: |
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Flashing |
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======== |
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Follow these steps if you just want to download the application to the board |
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SRAM and run. |
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``flash`` command is supported only by the Lauterbach TRACE32 runner: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: s32z2xxdc2/s32z270/rtu0 |
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:goals: build flash -r trace32 |
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:compact: |
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.. note:: |
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Currently, the Lauterbach start-up scripts executed with ``flash`` and |
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``debug`` commands perform the same steps to initialize the SoC and |
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load the application to SRAM. The difference is that ``flash`` hides the |
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Lauterbach TRACE32 interface, executes the application and exits. |
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To imitate a similar behavior using NXP S32 Debug Probe runner, you can run the |
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``debug`` command with GDB in batch mode: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: s32z2xxdc2/s32z270/rtu0 |
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:goals: build debug --tool-opt='--batch' |
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:compact: |
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RTU and Core Configuration |
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========================== |
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This Zephyr port can only run single core in any of the Cortex-R52 cores, |
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either in lock-step or split-lock mode. By default, Zephyr runs on the first |
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core of the RTU chosen and in lock-step mode (which is the reset |
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configuration). |
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To build for split-lock mode, the :kconfig:option:`CONFIG_DCLS` must be |
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disabled from your application Kconfig file. |
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By default the board configuration will set the runner arguments according to |
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the build configuration. To debug for a core different than the default use: |
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.. tabs:: |
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.. group-tab:: lockstep configuration |
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.. code-block:: console |
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west debug --core-name='R52_<rtu_id>_<core_id>_LS' |
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.. group-tab:: split-lock configuration |
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.. code-block:: console |
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west debug --core-name='R52_<rtu_id>_<core_id>' |
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Where: |
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- ``<rtu_id>`` is the zero-based RTU index |
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- ``<core_id>`` is the zero-based core index relative to the RTU on which to |
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run the Zephyr application (0, 1, 2 or 3) |
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For example, to build the :ref:`hello_world` sample for the board |
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``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: s32z2xxdc2/s32z270/rtu0 |
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:goals: build |
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:gen-args: -DCONFIG_DCLS=n |
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:compact: |
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To execute this sample in the second core of RTU0 in split-lock mode: |
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.. code-block:: console |
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west debug --core-name='R52_0_1' |
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If using Lauterbach TRACE32, all runner parameters must be overridden from command |
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line: |
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.. code-block:: console |
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west debug --startup-args elfFile=<elf_path> rtu=<rtu_id> core=<core_id> lockstep=<yes/no> |
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Where ``<elf_path>`` is the path to the Zephyr application ELF in the output |
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directory. |
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References |
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********** |
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.. target-notes:: |
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.. _NXP S32Z2 Real-Time Processors website: |
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https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32z-and-s32e-real-time-processors/s32z2-safe-and-secure-high-performance-real-time-processors:S32Z2 |
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.. _pySerial miniterm: |
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https://pyserial.readthedocs.io/en/latest/tools.html#module-serial.tools.miniterm
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