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86 lines
2.1 KiB
86 lines
2.1 KiB
/* |
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* Copyright (c) 2021 Intel Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/init.h> |
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#include <zephyr/kernel.h> |
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#include <ksched.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/sys/atomic.h> |
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#include <zephyr/arch/riscv/irq.h> |
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#include <zephyr/drivers/pm_cpu_ops.h> |
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#include <zephyr/platform/hooks.h> |
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volatile struct { |
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arch_cpustart_t fn; |
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void *arg; |
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} riscv_cpu_init[CONFIG_MP_MAX_NUM_CPUS]; |
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volatile uintptr_t __noinit riscv_cpu_wake_flag; |
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volatile uintptr_t riscv_cpu_boot_flag; |
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volatile void *riscv_cpu_sp; |
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extern void __start(void); |
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) |
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void soc_interrupt_init(void); |
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#endif |
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void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, |
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arch_cpustart_t fn, void *arg) |
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{ |
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riscv_cpu_init[cpu_num].fn = fn; |
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riscv_cpu_init[cpu_num].arg = arg; |
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riscv_cpu_sp = K_KERNEL_STACK_BUFFER(stack) + sz; |
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riscv_cpu_boot_flag = 0U; |
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#ifdef CONFIG_PM_CPU_OPS |
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if (pm_cpu_on(cpu_num, (uintptr_t)&__start)) { |
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printk("Failed to boot secondary CPU %d\n", cpu_num); |
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return; |
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} |
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#endif |
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while (riscv_cpu_boot_flag == 0U) { |
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riscv_cpu_wake_flag = _kernel.cpus[cpu_num].arch.hartid; |
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} |
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} |
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void arch_secondary_cpu_init(int hartid) |
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{ |
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unsigned int i; |
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unsigned int cpu_num = 0; |
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for (i = 0; i < CONFIG_MP_MAX_NUM_CPUS; i++) { |
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if (_kernel.cpus[i].arch.hartid == hartid) { |
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cpu_num = i; |
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} |
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} |
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csr_write(mscratch, &_kernel.cpus[cpu_num]); |
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#ifdef CONFIG_SMP |
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_kernel.cpus[cpu_num].arch.online = true; |
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#endif |
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#if defined(CONFIG_MULTITHREADING) && defined(CONFIG_THREAD_LOCAL_STORAGE) |
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__asm__("mv tp, %0" : : "r" (z_idle_threads[cpu_num].tls)); |
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#endif |
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) |
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soc_interrupt_init(); |
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#endif |
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#ifdef CONFIG_RISCV_PMP |
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z_riscv_pmp_init(); |
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#endif |
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#ifdef CONFIG_SMP |
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irq_enable(RISCV_IRQ_MSOFT); |
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#endif /* CONFIG_SMP */ |
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#ifdef CONFIG_PLIC_IRQ_AFFINITY |
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/* Enable on secondary cores so that they can respond to PLIC */ |
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irq_enable(RISCV_IRQ_MEXT); |
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#endif /* CONFIG_PLIC_IRQ_AFFINITY */ |
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#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK |
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soc_per_core_init_hook(); |
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#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ |
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riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg); |
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}
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