Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
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/*
* Copyright (c) 2022 Benjamin Björnsson <benjamin.bjornsson@gmail.com>.
* Copyright (c) 2024 DNDG srl
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <st/h7/stm32h747Xi_m7.dtsi>
#include <st/h7/stm32h747xihx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "arduino_opta-common.dtsi"
/ {
model = "Arduino OPTA M7 core Programmable Logic Controller";
compatible = "arduino,opta-m7";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
#include <../boards/common/usb/cdc_acm_serial.dtsi>
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
hse-bypass;
status = "okay";
};
&clk_lse {
clock-frequency = <32768>;
lse-bypass;
status = "okay";
};
&clk_hsi {
hsi-div = <1>;
status = "okay";
};
&clk_hsi48 {
/* HSI48 required for USB */
status = "okay";
};
&pll {
div-m = <5>;
mul-n = <160>;
div-p = <2>;
div-r = <2>;
div-q = <10>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(400)>;
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcu-boot";
reg = <0x00000000 DT_SIZE_K(256)>;
read-only;
};
slot0_partition: partition@40000 {
label = "image-0";
reg = <0x00040000 DT_SIZE_K(768)>;
};
};
};
/* Assign USB to M7 by default */
&usbotg_fs {
status = "okay";
};
&usbotg_hs {
status = "disabled";
};
/* Assign ethernet to M7 by default */
&mac {
pinctrl-0 = <
&eth_ref_clk_pa1
&eth_crs_dv_pa7
&eth_rxd0_pc4
&eth_rxd1_pc5
&eth_tx_en_pg11
&eth_txd1_pg12
&eth_txd0_pg13
>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
status = "okay";
};
&mdio {
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
pinctrl-names = "default";
status = "okay";
eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};