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271 lines
28 KiB
271 lines
28 KiB
.. zephyr:board:: max78000evkit |
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Overview |
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The MAX78000 evaluation kit (EV kit) provides a platform for leveraging the capabilities of the MAX78000 to build |
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new generations of artificial intelligence (AI) devices. Onboard hardware includes a digital microphone, a gyroscope/accelerometer, parallel camera module support |
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and a 3.5in touch-enabled color TFT display. A secondary display is driven by a power accumulator for tracking |
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device power consumption over time. Uncommitted GPIO as well as analog inputs are readily accessible through |
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0.1in pin headers. Primary system power as well as UART access is provided by a USB Micro-B connector. A USB |
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to SPI bridge provides rapid access to onboard memory, allowing large networks or images to load quickly |
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The Zephyr port is running on the MAX78000 MCU. |
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Hardware |
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- MAX78000 MCU: |
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- Dual-Core, Low-Power Microcontroller |
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- Arm Cortex-M4 Processor with FPU up to 100MHz |
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- 512KB Flash and 128KB SRAM |
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- Optimized Performance with 16KB Instruction Cache |
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- Optional Error Correction Code (ECC-SEC-DED) for SRAM |
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- 32-Bit RISC-V Coprocessor up to 60MHz |
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- Up to 52 General-Purpose I/O Pins |
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- 12-Bit Parallel Camera Interface |
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- One I2S Master/Slave for Digital Audio Interface |
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- Neural Network Accelerator |
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- Highly Optimized for Deep Convolutional Neural Networks |
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- 442k 8-Bit Weight Capacity with 1,2,4,8-Bit Weights |
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- Programmable Input Image Size up to 1024 x 1024 pixels |
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- Programmable Network Depth up to 64 Layers |
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- Programmable per Layer Network Channel Widths up to 1024 Channels |
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- 1 and 2 Dimensional Convolution Processing |
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- Streaming Mode |
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- Flexibility to Support Other Network Types, Including MLP and Recurrent Neural Networks |
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- Power Management Maximizes Operating Time for Battery Applications |
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- Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS) |
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- 2.0V to 3.6V SIMO Supply Voltage Range |
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- Dynamic Voltage Scaling Minimizes Active Core Power Consumption |
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- 22.2μA/MHz While Loop Execution at 3.0V from Cache (CM4 Only) |
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- Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled |
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- Security and Integrity |
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- Available Secure Boot |
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- AES 128/192/256 Hardware Acceleration Engine |
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- True Random Number Generator (TRNG) Seed Generator |
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Supported Features |
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================== |
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.. zephyr:board-supported-hw:: |
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Connections and IOs |
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=================== |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| Name | Name | Settings | Description | |
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+===========+===================+===================+==============================================================================================+ |
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| JP1 | LED1 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables auxiliary LED1 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables auxiliary LED1 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP2 | LED2 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables auxiliary LED2 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables auxiliary LED2 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP3 | TRIG1 | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables power monitor event trigger 1 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables power monitor event trigger 1 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP4 | TRIG2 | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables power monitor event trigger 2 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables power monitor event trigger 2 | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP5 | VREGI | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables 3V3 VREGI power | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables 3V3 VREGI power | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP6 | VREGIA | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables 3V3 VREGIA power | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables 3V3 VREGIA power | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP7 | CNN BOOST | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables 1V1 boost LDO power | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables 1V1 boost LDO power | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP8 | VDDA | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Internal SIMO powers VDDA | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 2-3 | | | External LDO powers VDDA | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP9 | VDDIO | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Internal SIMO powers VDDIO | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 2-3 | | | External LDO powers VDDIO | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP10 | VDDIOH | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | DUT LDO powers VDDIOH | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 2-3 | | | AUX LDO powers VDDIOH | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP11 | VCOREB | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Internal SIMO powers VCOREB | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 2-3 | | | External LDO powers VCOREB | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP12 | VCOREA | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Internal SIMO powers VCOREA | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 2-3 | | | External LDO powers VCOREA | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP13 | VREGI PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Bypasses power monitor shunt | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Enables power monitoring using power accumulator | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP14 | CNN 1V1 | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Connects 1V1 boost LDO to VCOREA | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables 1V1 boost LDO | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP15 | VCOREA PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Bypasses power monitor shunt | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Enables power monitoring using power accumulator | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP16 | VCOREB PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Bypasses power monitor shunt | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Enables power monitoring using power accumulator | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP17 | VREG_A PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Bypasses power monitor shunt | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Enables power monitoring using power accumulator | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP18 | RESET EN | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables RV JTAG adapter to perform full system reset | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables system reset by RV JTAG adapter | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP19 | TFT BL | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables main TFT screen backlight | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Disables main TFT screen backlight | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP20 | I2S CLK SEL | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Onboard 12.288MHz oscillator drives I2S clock | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 2-3 | | | External 1V8 CMOS LEVEL source drives I2S clock | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP21 | DUT I | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | DUT 3V3 total current monitor point | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | Open | | | Open to insert current meter | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JP22 | USB-SPI/CAM | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2 | | | Enables USB-SPI bridge | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 2-3 | | | Enables camera | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JH1 | UART 0 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | 1-2, 3-4 | | | Enables USB-UART0 bridge, software flow control | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | All Open | | | Disables USB-UART0 bridge, allows reuse of port pins | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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| JH2 | UART 1 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | |All installed | | | Enables USB-UART1 bridge | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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| | | | All Open | | | Disables USB-UART1 bridge, allows reuse of port pins | | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+ |
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Programming and Debugging |
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************************* |
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.. zephyr:board-supported-runners:: |
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Flashing |
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======== |
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The MAX78000 MCU can be flashed by connecting an external debug probe to the |
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SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH5. |
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Logic levels are fixed to VDDIO (1.8V). |
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Once the debug probe is connected to your host computer, then you can simply run the |
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``west flash`` command to write a firmware image into flash. To perform a full erase, |
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pass the ``--erase`` option when executing ``west flash``. |
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.. note:: |
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This board uses OpenOCD as the default debug interface. You can also use |
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a Segger J-Link with Segger's native tooling by overriding the runner, |
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appending ``--runner jlink`` to your ``west`` command(s). The J-Link should |
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be connected to the standard 2*5 pin debug connector (JH5) using an |
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appropriate adapter board and cable. |
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Debugging |
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========= |
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Please refer to the `Flashing`_ section and run the ``west debug`` command |
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instead of ``west flash``. |
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References |
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- `MAX78000EVKIT web page`_ |
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.. _MAX78000EVKIT web page: |
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https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78000evkit.html
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