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.. zephyr:board:: max32655evkit |
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Overview |
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The MAX32655 evaluation kit (EV kit) provides a platform for evaluation capabilities |
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of the MAX32655 microcontroller, which is an advanced system-on-chip (SoC). |
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It features an Arm® Cortex®-M4F CPU for efficient computation of complex functions and |
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algorithms, integrated power management (SIMO), and the newest generation |
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Bluetooth® 5.0 Low Energy (Bluetooth LE), long-range radio for wearable and hearable device applications. |
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The Zephyr port is running on the MAX32655 MCU. |
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.. image:: img/max32655evkit_img1.jpg |
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:align: center |
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:alt: MAX32655 EVKIT Front |
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.. image:: img/max32655evkit_img2.jpg |
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:align: center |
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:alt: MAX32655 Back |
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Hardware |
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- MAX32655 MCU: |
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- Ultra-Low-Power Wireless Microcontroller |
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- Internal 100MHz Oscillator |
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- Flexible Low-Power Modes with 7.3728MHz System Clock Option |
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- 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank) |
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- 16KB Instruction Cache |
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- Bluetooth 5.2 LE Radio |
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- Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing |
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- Fully Open-Source Bluetooth 5.2 Stack Available |
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- Supports AoA, AoD, LE Audio, and Mesh |
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- High-Throughput (2Mbps) Mode |
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- Long-Range (125kbps and 500kbps) Modes |
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- Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm |
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- Single-Ended Antenna Connection (50Ω) |
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- Power Management Maximizes Battery Life |
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- 2.0V to 3.6V Supply Voltage Range |
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- Integrated SIMO Power Regulator |
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- Dynamic Voltage Scaling (DVS) |
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- 23.8μA/MHz Active Current at 3.0V |
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- 4.4μA at 3.0V Retention Current for 32KB |
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- Selectable SRAM Retention + RTC in Low-Power Modes |
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- Multiple Peripherals for System Control |
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- Up to Two High-Speed SPI Master/Slave |
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- Up to Three High-Speed I2C Master/Slave (3.4Mbps) |
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- Up to Four UART, One I2S Master/Slave |
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- Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps |
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- Up to Four Micro-Power Comparators |
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- Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers |
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- 1-Wire® Master |
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- Up to Four Pulse Train (PWM) Engines |
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- RTC with Wake-Up Timer |
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- Up to 52 GPIOs |
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- Security and Integrity |
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- Available Secure Boot |
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- TRNG Seed Generator |
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- AES 128/192/256 Hardware Acceleration Engine |
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- External devices connected to the MAX32655 EVKIT: |
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- Color TFT Display |
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- Audio Stereo Codec Interface |
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- Digital Microphone |
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- A 128Mb QSPI flash |
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Supported Features |
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================== |
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.. zephyr:board-supported-hw:: |
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Connections and IOs |
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=================== |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| Name | Signal | Usage | |
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+===========+===============+=======================================================================+ |
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| JP1 | VREGI | Connect/Disconnect VREGIO power | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP2 | P0_24 | Enable/Disable LED1 | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP3 | P0_25 | Enable/Disable LED2 | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP4 | P2_6/ P2_7 | Connect/Disconnect the USB to serial UART to GPIO P2_6 (LPUART_RX) | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP5 | P2_7/ P0_1 | Connect/Disconnect the USB to serial UART to GPIO P2_7 (LPUART_TX) | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP6 | P0_2 | Connect/Disconnect the USB to serial UART to GPIO P0_2 (UART0_CTS) | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP7 | P0_3 | Connect/Disconnect he USB to serial UART to GPIO P0_3 (UART0_RTS) | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP8 | VREGI | Select VDDIO_EN power source (3V3 or coin cell) | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP9 | VDDIOH_EN | Select VDDIOH_EN power source 3V3/VREGI | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP10 | VDDIOH | Connect/Disconnect VDDIOH power | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP11 | VDDIO_EN | Select VDDIO_EN power source 1V8/VREGO_A | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP12 | VDDIO | Connect/Disconnect VDDIO power | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP13 | VDDA_EN | Select VDDA_EN power source 1V8/VREGO_A | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP14 | VDDA | Connect/Disconnect VDDA power | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP15 | VCOREA_EN | Select VCOREA_EN power source 1V1/VREGO_C | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP16 | VCOREA | Connect/Disconnect VCOREA power | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP17 | VCOREB_EN | Select VCOREB_EN power source 1V1/VREGO_B | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP18 | VCOREB | Connect/Disconnect VCOREB power | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP19 | BLE_LDO | Connect/Disconnect BLE_LDO power | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP20 | VREF | Select VREF power source VDDIO/VDDIOH | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP21 | I2C0_PU | Select I2C0_PU power source VDDIO/VDDIOH | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP22 | I2C1_PU | Select I2C1_PU power source VDDIO/VDDIOH | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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| JP23 | BOARD RESET | Connect/Disconnect RV JTAG NRESET from the BOARD RESET circuitry | |
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+-----------+---------------+-----------------------------------------------------------------------+ |
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Programming and Debugging |
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************************* |
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.. zephyr:board-supported-runners:: |
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Flashing |
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======== |
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The MAX32655 MCU can be flashed by connecting an external debug probe to the |
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SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH3. |
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Logic levels are fixed to VDDIO (1.8V). |
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Once the debug probe is connected to your host computer, then you can simply run the |
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``west flash`` command to write a firmware image into flash. To perform a full erase, |
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pass the ``--erase`` option when executing ``west flash``. |
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.. note:: |
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This board uses OpenOCD as the default debug interface. You can also use |
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a Segger J-Link with Segger's native tooling by overriding the runner, |
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appending ``--runner jlink`` to your ``west`` command(s). The J-Link should |
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be connected to the standard 2*5 pin debug connector (JW3) using an |
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appropriate adapter board and cable. |
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Debugging |
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========= |
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Please refer to the `Flashing`_ section and run the ``west debug`` command |
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instead of ``west flash``. |
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References |
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********** |
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- `MAX32655EVKIT web page`_ |
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.. _MAX32655EVKIT web page: |
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https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32655evkit.html#eb-overview
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