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148 lines
3.8 KiB
148 lines
3.8 KiB
/* ipm_quark_se.h - Quark SE mailbox driver */ |
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/* |
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* Copyright (c) 2015 Intel Corporation |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); |
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* you may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0 |
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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#ifndef __INCquark_se_mailboxh |
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#define __INCquark_se_mailboxh |
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#include <nanokernel.h> |
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#include <board.h> /* for SCSS_REGISTER_BASE */ |
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#include <ipm.h> |
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#include <device.h> |
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#include <init.h> |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#define QUARK_SE_IPM_OUTBOUND 0 |
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#define QUARK_SE_IPM_INBOUND 1 |
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#if defined(CONFIG_SOC_QUARK_SE) |
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/* First byte of the QUARK_SE_IPM_MASK register is for the Lakemont */ |
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#define QUARK_SE_IPM_MASK_START_BIT 0 |
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#define QUARK_SE_IPM_INTERRUPT 21 |
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#define QUARK_SE_IPM_ARC_LMT_DIR QUARK_SE_IPM_INBOUND |
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#define QUARK_SE_IPM_LMT_ARC_DIR QUARK_SE_IPM_OUTBOUND |
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#elif defined(CONFIG_SOC_QUARK_SE_SS) |
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/* Second byte is for ARC */ |
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#define QUARK_SE_IPM_MASK_START_BIT 8 |
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#define QUARK_SE_IPM_INTERRUPT 57 |
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#define QUARK_SE_IPM_ARC_LMT_DIR QUARK_SE_IPM_OUTBOUND |
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#define QUARK_SE_IPM_LMT_ARC_DIR QUARK_SE_IPM_INBOUND |
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#else |
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#error "Unsupported platform for ipm_quark_se driver" |
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#endif |
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#define QUARK_SE_IPM_CHANNELS 8 |
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#define QUARK_SE_IPM_DATA_BYTES (4 * sizeof(uint32_t)) |
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#define QUARK_SE_IPM_MAX_ID_VAL 0x7FFFFFFF |
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/* QUARK_SE EAS section 28.5.1.123 */ |
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struct __packed quark_se_ipm_ch_ctrl { |
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uint32_t ctrl : 31; |
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uint32_t irq : 1; |
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}; |
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struct __packed quark_se_ipm_ch_sts { |
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uint32_t sts : 1; |
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uint32_t irq : 1; |
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uint32_t reserved : 30; |
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}; |
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struct __packed quark_se_ipm { |
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struct quark_se_ipm_ch_ctrl ctrl; |
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uint8_t data[QUARK_SE_IPM_DATA_BYTES]; /* contiguous 32-bit registers */ |
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struct quark_se_ipm_ch_sts sts; |
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}; |
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/* Base address for mailboxes |
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* |
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* Layout: |
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* |
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* quark_se_ipm[8] |
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* QUARK_SE_IPM_CHALL_STS |
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*/ |
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#define QUARK_SE_IPM_BASE (SCSS_REGISTER_BASE + 0xa00) |
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/* 28.5.1.73 Host processor Interrupt routing mask 21 |
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* |
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* Bits Description |
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* 31:24 Mailbox SS Halt interrupt maskIUL |
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* 23:16 Mailbox Host Halt interrupt mask |
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* 15:8 Mailbox SS interrupt mask |
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* 7:0 Mailbox Host interrupt mask |
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*/ |
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#define QUARK_SE_IPM_MASK (SCSS_REGISTER_BASE + 0x4a0) |
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/* All status bits of the mailboxes |
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* |
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* Bits Description |
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* 31:16 Reserved |
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* 15:0 CHn_STS bits (sts/irq) for all channels |
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*/ |
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#define QUARK_SE_IPM_CHALL_STS (SCSS_REGISTER_BASE + 0x0AC0) |
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#define QUARK_SE_IPM(channel) ((volatile struct quark_se_ipm *)(QUARK_SE_IPM_BASE + \ |
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((channel) * sizeof(struct quark_se_ipm)))) |
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/* XXX I pulled this number out of thin air -- how to choose |
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* the right priority? |
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*/ |
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#define QUARK_SE_IPM_INTERRUPT_PRI 2 |
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struct quark_se_ipm_controller_config_info { |
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int (*controller_init)(void); |
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}; |
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struct quark_se_ipm_config_info { |
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int channel; |
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int direction; |
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volatile struct quark_se_ipm *ipm; |
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}; |
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struct quark_se_ipm_driver_data { |
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ipm_callback_t callback; |
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void *callback_ctx; |
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}; |
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void quark_se_ipm_isr(void *param); |
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int quark_se_ipm_initialize(struct device *d); |
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int quark_se_ipm_controller_initialize(struct device *d); |
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#define QUARK_SE_IPM_DEFINE(name, ch, dir) \ |
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struct quark_se_ipm_config_info quark_se_ipm_config_##name = { \ |
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.ipm = QUARK_SE_IPM(ch), \ |
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.channel = ch, \ |
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.direction = dir \ |
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}; \ |
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struct quark_se_ipm_driver_data quark_se_ipm_runtime_##name; \ |
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DEVICE_INIT(name, _STRINGIFY(name), quark_se_ipm_initialize, \ |
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&quark_se_ipm_runtime_##name, &quark_se_ipm_config_##name, \ |
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT) |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __INCquark_se_mailboxh */
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