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136 lines
3.8 KiB
136 lines
3.8 KiB
/* quark_se_clock_control.c - Clock controller driver for Quark SE */ |
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/* |
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* Copyright (c) 2015 Intel Corporation. |
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* |
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* Licensed under the Apache License, Version 2.0 (the "License"); |
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* you may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at |
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* |
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* http://www.apache.org/licenses/LICENSE-2.0 |
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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*/ |
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#include <nanokernel.h> |
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#include <arch/cpu.h> |
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#include <misc/__assert.h> |
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#include <board.h> |
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#include <device.h> |
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#include <init.h> |
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#include <sys_io.h> |
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#include <clock_control.h> |
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#include <clock_control/quark_se_clock_control.h> |
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#ifndef CONFIG_CLOCK_DEBUG |
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#define DBG(...) {; } |
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#else |
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#if defined(CONFIG_STDOUT_CONSOLE) |
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#include <stdio.h> |
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#define DBG printf |
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#else |
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#include <misc/printk.h> |
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#define DBG printk |
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#endif /* CONFIG_STDOUT_CONSOLE */ |
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#endif /* CONFIG_CLOCK_DEBUG */ |
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struct quark_se_clock_control_config { |
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uint32_t base_address; |
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}; |
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static inline int quark_se_clock_control_on(struct device *dev, |
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clock_control_subsys_t sub_system) |
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{ |
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struct quark_se_clock_control_config *info = dev->config->config_info; |
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uint32_t subsys = POINTER_TO_INT(sub_system); |
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if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) { |
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DBG("Enabling all clock gates on dev %p\n", dev); |
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sys_write32(0xffffffff, info->base_address); |
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return DEV_OK; |
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} |
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DBG("Enabling clock gate on dev %p subsystem %u\n", dev, subsys); |
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return sys_test_and_set_bit(info->base_address, subsys); |
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} |
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static inline int quark_se_clock_control_off(struct device *dev, |
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clock_control_subsys_t sub_system) |
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{ |
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struct quark_se_clock_control_config *info = dev->config->config_info; |
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uint32_t subsys = POINTER_TO_INT(sub_system); |
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if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) { |
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DBG("Disabling all clock gates on dev %p\n", dev); |
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sys_write32(0x00000000, info->base_address); |
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return DEV_OK; |
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} |
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DBG("clock gate on dev %p subsystem %u\n", dev, subsys); |
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return sys_test_and_clear_bit(info->base_address, subsys); |
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} |
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static struct clock_control_driver_api quark_se_clock_control_api = { |
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.on = quark_se_clock_control_on, |
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.off = quark_se_clock_control_off |
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}; |
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int quark_se_clock_control_init(struct device *dev) |
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{ |
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dev->driver_api = &quark_se_clock_control_api; |
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DBG("Quark Se clock controller driver initialized on device: %p\n", |
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dev); |
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return DEV_OK; |
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} |
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL |
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struct quark_se_clock_control_config clock_quark_se_peripheral_config = { |
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.base_address = CLOCK_PERIPHERAL_BASE_ADDR |
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}; |
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DEVICE_INIT(clock_quark_se_peripheral, |
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CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME, |
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&quark_se_clock_control_init, |
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NULL, &clock_quark_se_peripheral_config, |
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PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); |
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL */ |
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL |
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struct quark_se_clock_control_config clock_quark_se_external_config = { |
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.base_address = CLOCK_EXTERNAL_BASE_ADDR |
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}; |
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DEVICE_INIT(clock_quark_se_external, |
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CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME, |
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&quark_se_clock_control_init, |
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NULL, &clock_quark_se_external_config, |
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PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); |
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL */ |
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR |
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struct quark_se_clock_control_config clock_quark_se_sensor_config = { |
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.base_address = CLOCK_SENSOR_BASE_ADDR |
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}; |
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DEVICE_INIT(clock_quark_se_sensor, |
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CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME, |
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&quark_se_clock_control_init, |
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NULL, &clock_quark_se_sensor_config, |
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PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); |
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR */
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