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18 lines
528 B
18 lines
528 B
# Texas Instruments MSPM0 Family |
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# Copyright (c) 2025 Texas Instruments |
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# Copyright (c) 2025 Linumiz |
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# SPDX-License-Identifier: Apache-2.0 |
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if SOC_FAMILY_TI_MSPM0 |
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rsource "*/Kconfig" |
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# Per TRM Section 2.2.7 Peripheral Power Enable Control: wait at least 4 ULPCLK |
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# clock cycles before accessing the peripheral's memory-mapped registers. |
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# ULPCLK will either be equivalent or half of the main MCLK and CPUCLK, |
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# yielding the delay time of 8 cycles |
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config MSPM0_PERIPH_STARTUP_DELAY |
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int |
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default 8 |
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endif # SOC_FAMILY_TI_MSPM0
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