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544 lines
14 KiB
544 lines
14 KiB
/* |
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* Copyright (c) 2019-2020 Cobham Gaisler AB |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT gaisler_apbuart |
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#include <drivers/uart.h> |
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#include <errno.h> |
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/* APBUART registers |
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* |
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* Offset | Name | Description |
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* ------ | ------ | ---------------------------------------- |
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* 0x0000 | data | UART data register |
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* 0x0004 | status | UART status register |
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* 0x0008 | ctrl | UART control register |
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* 0x000c | scaler | UART scaler register |
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* 0x0010 | debug | UART FIFO debug register |
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*/ |
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struct apbuart_regs { |
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/** @brief UART data register |
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* |
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* Bit | Name | Description |
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* ------ | ------ | ---------------------------------------- |
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* 7-0 | data | Holding register or FIFO |
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*/ |
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uint32_t data; /* 0x0000 */ |
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/** @brief UART status register |
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* |
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* Bit | Name | Description |
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* ------ | ------ | ---------------------------------------- |
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* 31-26 | RCNT | Receiver FIFO count |
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* 25-20 | TCNT | Transmitter FIFO count |
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* 10 | RF | Receiver FIFO full |
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* 9 | TF | Transmitter FIFO full |
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* 8 | RH | Receiver FIFO half-full |
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* 7 | TH | Transmitter FIFO half-full |
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* 6 | FE | Framing error |
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* 5 | PE | Parity error |
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* 4 | OV | Overrun |
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* 3 | BR | Break received |
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* 2 | TE | Transmitter FIFO empty |
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* 1 | TS | Transmitter shift register empty |
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* 0 | DR | Data ready |
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*/ |
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uint32_t status; /* 0x0004 */ |
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/** @brief UART control register |
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* |
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* Bit | Name | Description |
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* ------ | ------ | ---------------------------------------- |
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* 31 | FA | FIFOs available |
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* 14 | SI | Transmitter shift register empty interrupt enable |
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* 13 | DI | Delayed interrupt enable |
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* 12 | BI | Break interrupt enable |
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* 11 | DB | FIFO debug mode enable |
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* 10 | RF | Receiver FIFO interrupt enable |
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* 9 | TF | Transmitter FIFO interrupt enable |
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* 8 | EC | External clock |
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* 7 | LB | Loop back |
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* 6 | FL | Flow control |
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* 5 | PE | Parity enable |
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* 4 | PS | Parity select |
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* 3 | TI | Transmitter interrupt enable |
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* 2 | RI | Receiver interrupt enable |
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* 1 | TE | Transmitter enable |
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* 0 | RE | Receiver enable |
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*/ |
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uint32_t ctrl; /* 0x0008 */ |
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/** @brief UART scaler register |
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* |
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* Bit | Name | Description |
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* ------ | ------ | ---------------------------------------- |
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* 11-0 | RELOAD | Scaler reload value |
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*/ |
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uint32_t scaler; /* 0x000c */ |
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/** @brief UART FIFO debug register |
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* |
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* Bit | Name | Description |
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* ------ | ------ | ---------------------------------------- |
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* 7-0 | data | Holding register or FIFO |
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*/ |
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uint32_t debug; /* 0x0010 */ |
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}; |
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/* APBUART register bits. */ |
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/* Control register */ |
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#define APBUART_CTRL_FA (1 << 31) |
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#define APBUART_CTRL_DB (1 << 11) |
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#define APBUART_CTRL_RF (1 << 10) |
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#define APBUART_CTRL_TF (1 << 9) |
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#define APBUART_CTRL_LB (1 << 7) |
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#define APBUART_CTRL_FL (1 << 6) |
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#define APBUART_CTRL_PE (1 << 5) |
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#define APBUART_CTRL_PS (1 << 4) |
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#define APBUART_CTRL_TI (1 << 3) |
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#define APBUART_CTRL_RI (1 << 2) |
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#define APBUART_CTRL_TE (1 << 1) |
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#define APBUART_CTRL_RE (1 << 0) |
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/* Status register */ |
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#define APBUART_STATUS_RF (1 << 10) |
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#define APBUART_STATUS_TF (1 << 9) |
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#define APBUART_STATUS_RH (1 << 8) |
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#define APBUART_STATUS_TH (1 << 7) |
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#define APBUART_STATUS_FE (1 << 6) |
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#define APBUART_STATUS_PE (1 << 5) |
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#define APBUART_STATUS_OV (1 << 4) |
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#define APBUART_STATUS_BR (1 << 3) |
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#define APBUART_STATUS_TE (1 << 2) |
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#define APBUART_STATUS_TS (1 << 1) |
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#define APBUART_STATUS_DR (1 << 0) |
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/* For APBUART implemented without FIFO */ |
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#define APBUART_STATUS_HOLD_REGISTER_EMPTY (1 << 2) |
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struct apbuart_dev_cfg { |
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struct apbuart_regs *regs; |
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int interrupt; |
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}; |
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struct apbuart_dev_data { |
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int usefifo; |
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN |
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uart_irq_callback_user_data_t cb; |
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void *cb_data; |
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#endif |
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}; |
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#define DEV_CFG(dev) \ |
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((const struct apbuart_dev_cfg *const)(dev)->config) |
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#define DEV_DATA(dev) \ |
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((struct apbuart_dev_data *const)(dev)->data) |
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/* |
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* This routine waits for the TX holding register or TX FIFO to be ready and |
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* then it writes a character to the data register. |
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*/ |
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static void apbuart_poll_out(const struct device *dev, unsigned char x) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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if (DEV_DATA(dev)->usefifo) { |
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/* Transmitter FIFO full flag is available. */ |
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while (regs->status & APBUART_STATUS_TF) { |
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; |
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} |
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} else { |
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/* |
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* Transmitter "hold register empty" AKA "FIFO empty" flag is |
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* available. |
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*/ |
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while (!(regs->status & APBUART_STATUS_HOLD_REGISTER_EMPTY)) { |
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; |
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} |
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} |
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regs->data = x & 0xff; |
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} |
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static int apbuart_poll_in(const struct device *dev, unsigned char *c) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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if ((regs->status & APBUART_STATUS_DR) == 0) { |
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return -1; |
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} |
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*c = regs->data & 0xff; |
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return 0; |
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} |
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static int apbuart_err_check(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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const uint32_t status = regs->status; |
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int err = 0; |
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if (status & APBUART_STATUS_FE) { |
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err |= UART_ERROR_FRAMING; |
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} |
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if (status & APBUART_STATUS_PE) { |
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err |= UART_ERROR_PARITY; |
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} |
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if (status & APBUART_STATUS_OV) { |
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err |= UART_ERROR_OVERRUN; |
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} |
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if (status & APBUART_STATUS_BR) { |
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err |= UART_BREAK; |
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} |
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return err; |
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} |
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE |
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static int get_baud(volatile struct apbuart_regs *const regs) |
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{ |
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unsigned int core_clk_hz; |
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unsigned int scaler; |
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scaler = regs->scaler; |
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core_clk_hz = sys_clock_hw_cycles_per_sec(); |
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/* Calculate baud rate from generator "scaler" number */ |
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return core_clk_hz / ((scaler + 1) * 8); |
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} |
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static void set_baud(volatile struct apbuart_regs *const regs, uint32_t baud) |
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{ |
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unsigned int core_clk_hz; |
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unsigned int scaler; |
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if (baud == 0) { |
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return; |
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} |
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core_clk_hz = sys_clock_hw_cycles_per_sec(); |
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/* Calculate Baud rate generator "scaler" number */ |
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scaler = (((core_clk_hz * 10) / (baud * 8)) - 5) / 10; |
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/* Set new baud rate by setting scaler */ |
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regs->scaler = scaler; |
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} |
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static int apbuart_configure(const struct device *dev, |
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const struct uart_config *cfg) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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uint32_t ctrl = 0; |
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uint32_t newctrl = 0; |
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switch (cfg->parity) { |
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case UART_CFG_PARITY_NONE: |
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break; |
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case UART_CFG_PARITY_EVEN: |
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newctrl |= APBUART_CTRL_PE; |
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break; |
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case UART_CFG_PARITY_ODD: |
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newctrl |= APBUART_CTRL_PE | APBUART_CTRL_PS; |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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if (cfg->stop_bits != UART_CFG_STOP_BITS_1) { |
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return -ENOTSUP; |
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} |
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if (cfg->data_bits != UART_CFG_DATA_BITS_8) { |
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return -ENOTSUP; |
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} |
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switch (cfg->flow_ctrl) { |
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case UART_CFG_FLOW_CTRL_NONE: |
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break; |
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case UART_CFG_FLOW_CTRL_RTS_CTS: |
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newctrl |= APBUART_CTRL_FL; |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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set_baud(regs, cfg->baudrate); |
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ctrl = regs->ctrl; |
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ctrl &= ~(APBUART_CTRL_PE | APBUART_CTRL_PS | APBUART_CTRL_FL); |
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regs->ctrl = ctrl | newctrl; |
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return 0; |
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} |
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static int apbuart_config_get(const struct device *dev, struct uart_config *cfg) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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const uint32_t ctrl = regs->ctrl; |
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cfg->parity = UART_CFG_PARITY_NONE; |
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if (ctrl & APBUART_CTRL_PE) { |
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if (ctrl & APBUART_CTRL_PS) { |
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cfg->parity = UART_CFG_PARITY_ODD; |
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} else { |
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cfg->parity = UART_CFG_PARITY_EVEN; |
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} |
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} |
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_NONE; |
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if (ctrl & APBUART_CTRL_FL) { |
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS; |
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} |
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cfg->baudrate = get_baud(regs); |
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cfg->data_bits = UART_CFG_DATA_BITS_8; |
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cfg->stop_bits = UART_CFG_STOP_BITS_1; |
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return 0; |
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} |
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ |
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN |
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static void apbuart_isr(const struct device *dev); |
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static int apbuart_fifo_fill(const struct device *dev, const uint8_t *tx_data, |
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int size) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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int i; |
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if (DEV_DATA(dev)->usefifo) { |
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/* Transmitter FIFO full flag is available. */ |
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for ( |
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i = 0; |
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(i < size) && !(regs->status & APBUART_STATUS_TF); |
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i++ |
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) { |
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regs->data = tx_data[i]; |
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} |
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return i; |
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} |
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for (i = 0; (i < size) && (regs->status & APBUART_STATUS_TE); i++) { |
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regs->data = tx_data[i]; |
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} |
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return i; |
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} |
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static int apbuart_fifo_read(const struct device *dev, uint8_t *rx_data, |
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const int size) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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int i; |
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for (i = 0; (i < size) && (regs->status & APBUART_STATUS_DR); i++) { |
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rx_data[i] = regs->data & 0xff; |
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} |
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return i; |
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} |
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static void apbuart_irq_tx_enable(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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unsigned int key; |
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if (DEV_DATA(dev)->usefifo) { |
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/* Enable the FIFO level interrupt */ |
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regs->ctrl |= APBUART_CTRL_TF; |
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return; |
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} |
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regs->ctrl |= APBUART_CTRL_TI; |
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/* |
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* The "TI" interrupt is an edge interrupt. It fires each time the TX |
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* holding register (or FIFO if implemented) moves from non-empty to |
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* empty. |
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* |
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* When the APBUART is implemented _without_ FIFO, the TI interrupt is |
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* the only TX interrupt we have. When the APBUART is implemented |
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* _with_ FIFO, the TI will fire on each TX byte. |
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*/ |
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regs->ctrl |= APBUART_CTRL_TI; |
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/* Fire the first "TI" edge interrupt to get things going. */ |
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key = irq_lock(); |
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apbuart_isr(dev); |
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irq_unlock(key); |
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} |
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static void apbuart_irq_tx_disable(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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regs->ctrl &= ~(APBUART_CTRL_TF | APBUART_CTRL_TI); |
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} |
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static int apbuart_irq_tx_ready(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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if (DEV_DATA(dev)->usefifo) { |
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return !(regs->status & APBUART_STATUS_TF); |
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} |
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return !!(regs->status & APBUART_STATUS_TE); |
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} |
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static int apbuart_irq_tx_complete(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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return !!(regs->status & APBUART_STATUS_TS); |
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} |
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static void apbuart_irq_rx_enable(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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regs->ctrl |= APBUART_CTRL_RI; |
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} |
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static void apbuart_irq_rx_disable(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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regs->ctrl &= ~APBUART_CTRL_RI; |
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} |
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static int apbuart_irq_rx_ready(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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return !!(regs->status & APBUART_STATUS_DR); |
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} |
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static int apbuart_irq_is_pending(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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uint32_t status = regs->status; |
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uint32_t ctrl = regs->ctrl; |
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if ((ctrl & APBUART_CTRL_RI) && (status & APBUART_STATUS_DR)) { |
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return 1; |
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} |
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if (DEV_DATA(dev)->usefifo) { |
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/* TH is the TX FIFO half-empty flag */ |
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if (status & APBUART_STATUS_TH) { |
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return 1; |
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} |
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} else { |
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if ((ctrl & APBUART_CTRL_TI) && (status & APBUART_STATUS_TE)) { |
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return 1; |
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} |
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} |
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return 0; |
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} |
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static int apbuart_irq_update(const struct device *dev) |
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{ |
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return 1; |
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} |
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static void apbuart_irq_callback_set(const struct device *dev, |
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uart_irq_callback_user_data_t cb, |
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void *cb_data) |
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{ |
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struct apbuart_dev_data *const dev_data = DEV_DATA(dev); |
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dev_data->cb = cb; |
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dev_data->cb_data = cb_data; |
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} |
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static void apbuart_isr(const struct device *dev) |
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{ |
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struct apbuart_dev_data *const dev_data = DEV_DATA(dev); |
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if (dev_data->cb) { |
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dev_data->cb(dev, dev_data->cb_data); |
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} |
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} |
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ |
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static int apbuart_init(const struct device *dev) |
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{ |
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volatile struct apbuart_regs *regs = (void *) DEV_CFG(dev)->regs; |
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const uint32_t APBUART_DEBUG_MASK = APBUART_CTRL_DB | APBUART_CTRL_FL; |
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uint32_t dm; |
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uint32_t ctrl; |
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ctrl = regs->ctrl; |
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DEV_DATA(dev)->usefifo = !!(ctrl & APBUART_CTRL_FA); |
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/* NOTE: CTRL_FL has reset value 0. CTRL_DB has no reset value. */ |
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dm = ctrl & APBUART_DEBUG_MASK; |
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if (dm == APBUART_DEBUG_MASK) { |
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/* Debug mode enabled so assume APBUART already initialized. */ |
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; |
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} else { |
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regs->ctrl = APBUART_CTRL_TE | APBUART_CTRL_RE; |
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} |
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regs->status = 0; |
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN |
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irq_connect_dynamic(DEV_CFG(dev)->interrupt, |
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0, (void (*)(const void *))apbuart_isr, dev, 0); |
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irq_enable(DEV_CFG(dev)->interrupt); |
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#endif |
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return 0; |
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} |
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/* Driver API defined in uart.h */ |
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static const struct uart_driver_api apbuart_driver_api = { |
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.poll_in = apbuart_poll_in, |
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.poll_out = apbuart_poll_out, |
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.err_check = apbuart_err_check, |
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE |
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.configure = apbuart_configure, |
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.config_get = apbuart_config_get, |
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#endif |
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN |
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.fifo_fill = apbuart_fifo_fill, |
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.fifo_read = apbuart_fifo_read, |
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.irq_tx_enable = apbuart_irq_tx_enable, |
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.irq_tx_disable = apbuart_irq_tx_disable, |
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.irq_tx_ready = apbuart_irq_tx_ready, |
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.irq_rx_enable = apbuart_irq_rx_enable, |
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.irq_rx_disable = apbuart_irq_rx_disable, |
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.irq_tx_complete = apbuart_irq_tx_complete, |
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.irq_rx_ready = apbuart_irq_rx_ready, |
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.irq_is_pending = apbuart_irq_is_pending, |
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.irq_update = apbuart_irq_update, |
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.irq_callback_set = apbuart_irq_callback_set, |
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#endif |
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}; |
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#define APBUART_INIT(index) \ |
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static const struct apbuart_dev_cfg apbuart##index##_config = { \ |
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.regs = (struct apbuart_regs *) \ |
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DT_INST_REG_ADDR(index), \ |
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.interrupt = DT_INST_IRQN(index), \ |
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}; \ |
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\ |
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static struct apbuart_dev_data apbuart##index##_data = { \ |
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.usefifo = 0, \ |
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}; \ |
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\ |
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DEVICE_DT_INST_DEFINE(index, \ |
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&apbuart_init, \ |
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NULL, \ |
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&apbuart##index##_data, \ |
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&apbuart##index##_config, \ |
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PRE_KERNEL_1, \ |
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CONFIG_SERIAL_INIT_PRIORITY, \ |
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&apbuart_driver_api); |
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DT_INST_FOREACH_STATUS_OKAY(APBUART_INIT)
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