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370 lines
10 KiB
370 lines
10 KiB
/* |
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* Copyright (c) 2021 Andes Technology Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** |
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* @file GPIO driver for the AndesTech ATCGPIO100 controller |
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*/ |
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#include <errno.h> |
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#include <stdbool.h> |
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#include <kernel.h> |
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#include <device.h> |
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#include <soc.h> |
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#include <drivers/gpio.h> |
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#include <sys/util.h> |
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#include <sys/sys_io.h> |
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#include "gpio_utils.h" |
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#define DT_DRV_COMPAT andestech_atcgpio100 |
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/* Andes ATCGPIO100 register definition */ |
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#define REG_IDR 0x00 /* ID and Revision reg. */ |
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#define REG_CFG 0x10 /* Hardware configure reg. */ |
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#define REG_DIN 0x20 /* Data In reg. */ |
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#define REG_DOUT 0x24 /* Data Out reg. */ |
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#define REG_DIR 0x28 /* Channel direction reg. */ |
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#define REG_DCLR 0x2C /* Data out clear reg. */ |
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#define REG_DSET 0x30 /* Data out set reg. */ |
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#define REG_PUEN 0x40 /* Pull enable reg. */ |
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#define REG_PTYP 0x44 /* Pull type reg. */ |
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#define REG_INTE 0x50 /* Interrupt enable reg. */ |
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#define REG_IMD0 0x54 /* Interrupt mode 0 ~ 7 reg. */ |
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#define REG_IMD1 0x58 /* Interrupt mode 8 ~ 15 reg. */ |
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#define REG_IMD2 0x5C /* Interrupt mode 16 ~ 23 reg. */ |
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#define REG_IMD3 0x60 /* Interrupt mode 24 ~ 31 reg. */ |
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#define REG_ISTA 0x64 /* Interrupt status reg. */ |
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#define REG_DEBE 0x70 /* De-bounce enable reg. */ |
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#define REG_DEBC 0x74 /* De-Bounce control reg. */ |
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#define INT_NO_OPERATION 0x0 |
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#define INT_HIGH_LEVEL 0x2 |
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#define INT_LOW_LEVEL 0x3 |
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#define INT_NEGATIVE_EDGE 0x5 |
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#define INT_POSITIVE_EDGE 0x6 |
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#define INT_DUAL_EDGE 0x7 |
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#define PULL_CONFIGURED BIT(31) |
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#define DEBOUNCE_CONFIGURED BIT(29) |
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#define DF_DEBOUNCED_SETTING (0x80000003) |
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#define DEV_CFG(dev) \ |
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((const struct gpio_atcgpio100_config * const)(dev)->config) |
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#define DEV_DATA(dev) \ |
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((struct gpio_atcgpio100_data *)(dev)->data) |
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#define GPIO_CFG(dev) (DEV_CFG(dev)->base + REG_CFG) |
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#define GPIO_DIR(dev) (DEV_CFG(dev)->base + REG_DIR) |
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#define GPIO_DIN(dev) (DEV_CFG(dev)->base + REG_DIN) |
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#define GPIO_DOUT(dev) (DEV_CFG(dev)->base + REG_DOUT) |
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#define GPIO_DCLR(dev) (DEV_CFG(dev)->base + REG_DCLR) |
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#define GPIO_DSET(dev) (DEV_CFG(dev)->base + REG_DSET) |
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#define GPIO_PUEN(dev) (DEV_CFG(dev)->base + REG_PUEN) |
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#define GPIO_PTYP(dev) (DEV_CFG(dev)->base + REG_PTYP) |
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#define GPIO_INTE(dev) (DEV_CFG(dev)->base + REG_INTE) |
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#define GPIO_IMD(dev, idx) (DEV_CFG(dev)->base + REG_IMD0 + (idx * 4)) |
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#define GPIO_ISTA(dev) (DEV_CFG(dev)->base + REG_ISTA) |
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#define GPIO_DEBE(dev) (DEV_CFG(dev)->base + REG_DEBE) |
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#define GPIO_DEBC(dev) (DEV_CFG(dev)->base + REG_DEBC) |
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#define INWORD(x) sys_read32(x) |
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#define OUTWORD(x, d) sys_write32(d, x) |
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#define SET_GPIO_INT_MODE(cur_val, mode, ch_idx) \ |
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do { \ |
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cur_val &= ~(BIT_MASK(3) << (ch_idx * 4)); \ |
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cur_val |= (mode << (ch_idx * 4)); \ |
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} while (false) |
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typedef void (*atcgpio100_cfg_func_t)(void); |
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struct gpio_atcgpio100_config { |
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/* gpio_driver_config needs to be first */ |
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struct gpio_driver_config common; |
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uint32_t base; |
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uint32_t irq_num; |
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atcgpio100_cfg_func_t cfg_func; |
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}; |
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struct gpio_atcgpio100_data { |
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/* gpio_driver_data needs to be first */ |
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struct gpio_driver_data common; |
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/* list of callbacks */ |
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sys_slist_t cb; |
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struct k_spinlock lock; |
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}; |
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static int gpio_atcgpio100_config(const struct device *port, |
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gpio_pin_t pin, |
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gpio_flags_t flags) |
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{ |
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struct gpio_atcgpio100_data * const data = DEV_DATA(port); |
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uint32_t port_value, pin_mask, io_flags; |
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k_spinlock_key_t key; |
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/* Does not support disconnected pin, and |
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* not supporting both input/output at same time. |
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*/ |
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io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT); |
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if ((io_flags == GPIO_DISCONNECTED) |
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|| (io_flags == (GPIO_INPUT | GPIO_OUTPUT))) { |
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return -ENOTSUP; |
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} |
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pin_mask = BIT(pin); |
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if (flags & GPIO_OUTPUT) { |
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if (flags & GPIO_OUTPUT_INIT_HIGH) { |
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OUTWORD(GPIO_DSET(port), pin_mask); |
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} else if (flags & GPIO_OUTPUT_INIT_LOW) { |
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OUTWORD(GPIO_DCLR(port), pin_mask); |
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} |
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key = k_spin_lock(&data->lock); |
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/* Set channel output */ |
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port_value = INWORD(GPIO_DIR(port)); |
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OUTWORD(GPIO_DIR(port), port_value | pin_mask); |
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k_spin_unlock(&data->lock, key); |
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} else if (flags & GPIO_INPUT) { |
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if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) { |
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return -ENOTSUP; |
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} |
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key = k_spin_lock(&data->lock); |
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/* Set de-bounce */ |
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if (flags & GPIO_INT_DEBOUNCE) { |
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/* Default settings: Filter out pulses which are |
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* less than 4 de-bounce clock period |
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*/ |
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OUTWORD(GPIO_DEBC(port), DF_DEBOUNCED_SETTING); |
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port_value = INWORD(GPIO_DEBE(port)); |
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OUTWORD(GPIO_DEBE(port), port_value | pin_mask); |
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} |
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/* Set channel input */ |
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port_value = INWORD(GPIO_DIR(port)); |
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OUTWORD(GPIO_DIR(port), port_value & ~pin_mask); |
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k_spin_unlock(&data->lock, key); |
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} else { |
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return -ENOTSUP; |
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} |
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return 0; |
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} |
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static int gpio_atcgpio100_port_get_raw(const struct device *port, |
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gpio_port_value_t *value) |
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{ |
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*value = INWORD(GPIO_DIN(port)); |
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return 0; |
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} |
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static int gpio_atcgpio100_set_masked_raw(const struct device *port, |
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gpio_port_pins_t mask, |
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gpio_port_value_t value) |
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{ |
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struct gpio_atcgpio100_data * const data = DEV_DATA(port); |
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uint32_t port_value; |
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k_spinlock_key_t key = k_spin_lock(&data->lock); |
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port_value = INWORD(GPIO_DOUT(port)); |
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OUTWORD(GPIO_DOUT(port), (port_value & ~mask) | (value & mask)); |
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k_spin_unlock(&data->lock, key); |
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return 0; |
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} |
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static int gpio_atcgpio100_set_bits_raw(const struct device *port, |
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gpio_port_pins_t pins) |
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{ |
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OUTWORD(GPIO_DSET(port), pins); |
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return 0; |
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} |
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static int gpio_atcgpio100_clear_bits_raw(const struct device *port, |
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gpio_port_pins_t pins) |
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{ |
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OUTWORD(GPIO_DCLR(port), pins); |
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return 0; |
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} |
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static int gpio_atcgpio100_toggle_bits(const struct device *port, |
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gpio_port_pins_t pins) |
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{ |
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struct gpio_atcgpio100_data * const data = DEV_DATA(port); |
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uint32_t port_value; |
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k_spinlock_key_t key = k_spin_lock(&data->lock); |
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port_value = INWORD(GPIO_DOUT(port)); |
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OUTWORD(GPIO_DOUT(port), port_value ^ pins); |
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k_spin_unlock(&data->lock, key); |
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return 0; |
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} |
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static int gpio_atcgpio100_pin_interrupt_configure( |
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const struct device *port, |
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gpio_pin_t pin, |
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enum gpio_int_mode mode, |
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enum gpio_int_trig trig) |
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{ |
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struct gpio_atcgpio100_data * const data = DEV_DATA(port); |
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uint32_t port_value, int_mode, imr_idx, ch_idx; |
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k_spinlock_key_t key; |
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switch (mode | trig) { |
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case GPIO_INT_EDGE_BOTH: |
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int_mode = INT_DUAL_EDGE; |
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break; |
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case GPIO_INT_EDGE_RISING: |
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int_mode = INT_POSITIVE_EDGE; |
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break; |
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case GPIO_INT_EDGE_FALLING: |
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int_mode = INT_NEGATIVE_EDGE; |
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break; |
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case GPIO_INT_LEVEL_LOW: |
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int_mode = INT_LOW_LEVEL; |
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break; |
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case GPIO_INT_LEVEL_HIGH: |
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int_mode = INT_HIGH_LEVEL; |
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break; |
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default: |
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int_mode = INT_NO_OPERATION; |
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break; |
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} |
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imr_idx = (pin / 8); |
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ch_idx = (pin % 8); |
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key = k_spin_lock(&data->lock); |
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if (int_mode == INT_NO_OPERATION) { |
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/* Disable interrupt of pin */ |
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port_value = INWORD(GPIO_INTE(port)); |
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OUTWORD(GPIO_INTE(port), port_value & ~BIT(pin)); |
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/* Clear the remain pending interrupt */ |
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port_value = INWORD(GPIO_ISTA(port)); |
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OUTWORD(GPIO_ISTA(port), port_value); |
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} else { |
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/* Set interrupt mode of pin */ |
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port_value = INWORD(GPIO_IMD(port, imr_idx)); |
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SET_GPIO_INT_MODE(port_value, int_mode, ch_idx); |
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OUTWORD(GPIO_IMD(port, imr_idx), port_value); |
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/* Enable interrupt of pin */ |
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port_value = INWORD(GPIO_INTE(port)); |
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OUTWORD(GPIO_INTE(port), port_value | BIT(pin)); |
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} |
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k_spin_unlock(&data->lock, key); |
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return 0; |
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} |
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static int gpio_atcgpio100_manage_callback(const struct device *port, |
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struct gpio_callback *callback, |
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bool set) |
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{ |
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struct gpio_atcgpio100_data * const data = DEV_DATA(port); |
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return gpio_manage_callback(&data->cb, callback, set); |
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} |
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static void gpio_atcgpio100_irq_handler(const struct device *port) |
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{ |
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struct gpio_atcgpio100_data * const data = DEV_DATA(port); |
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uint32_t port_value; |
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port_value = INWORD(GPIO_ISTA(port)); |
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OUTWORD(GPIO_ISTA(port), port_value); |
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gpio_fire_callbacks(&data->cb, port, port_value); |
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} |
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static const struct gpio_driver_api gpio_atcgpio100_api = { |
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.pin_configure = gpio_atcgpio100_config, |
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.port_get_raw = gpio_atcgpio100_port_get_raw, |
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.port_set_masked_raw = gpio_atcgpio100_set_masked_raw, |
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.port_set_bits_raw = gpio_atcgpio100_set_bits_raw, |
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.port_clear_bits_raw = gpio_atcgpio100_clear_bits_raw, |
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.port_toggle_bits = gpio_atcgpio100_toggle_bits, |
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.pin_interrupt_configure = gpio_atcgpio100_pin_interrupt_configure, |
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.manage_callback = gpio_atcgpio100_manage_callback |
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}; |
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static int gpio_atcgpio100_init(const struct device *port) |
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{ |
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const struct gpio_atcgpio100_config * const dev_cfg = DEV_CFG(port); |
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/* Disable all interrupts */ |
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OUTWORD(GPIO_INTE(port), BIT_MASK(0)); |
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/* Write 1 to clear interrupt status */ |
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OUTWORD(GPIO_ISTA(port), (uint32_t) BIT64_MASK(32)); |
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/* Configure GPIO device */ |
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dev_cfg->cfg_func(); |
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/* Enable PLIC interrupt GPIO source */ |
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irq_enable(dev_cfg->irq_num); |
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return 0; |
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} |
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#define GPIO_ATCGPIO100_INIT(n) \ |
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static void gpio_atcgpio100_cfg_func_##n(void); \ |
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static struct gpio_atcgpio100_data gpio_atcgpio100_data_##n; \ |
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\ |
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static const struct gpio_atcgpio100_config \ |
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gpio_atcgpio100_config_##n = { \ |
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.common = { \ |
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.port_pin_mask = \ |
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GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \ |
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}, \ |
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.base = DT_INST_REG_ADDR(n), \ |
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.irq_num = DT_INST_IRQN(n), \ |
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.cfg_func = gpio_atcgpio100_cfg_func_##n \ |
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}; \ |
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\ |
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DEVICE_DT_INST_DEFINE(n, \ |
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gpio_atcgpio100_init, \ |
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NULL, \ |
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&gpio_atcgpio100_data_##n, \ |
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&gpio_atcgpio100_config_##n, \ |
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POST_KERNEL, \ |
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CONFIG_GPIO_INIT_PRIORITY, \ |
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&gpio_atcgpio100_api); \ |
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\ |
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static void gpio_atcgpio100_cfg_func_##n(void) \ |
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{ \ |
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IRQ_CONNECT(DT_INST_IRQN(n), \ |
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DT_INST_IRQ(n, priority), \ |
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gpio_atcgpio100_irq_handler, \ |
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DEVICE_DT_INST_GET(n), \ |
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0); \ |
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return; \ |
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} \ |
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DT_INST_FOREACH_STATUS_OKAY(GPIO_ATCGPIO100_INIT)
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