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730 lines
21 KiB
730 lines
21 KiB
/* |
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* Copyright (c) 2017 Linaro Limited. |
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* Copyright (c) 2017 RnDity Sp. z o.o. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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|
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#include <soc.h> |
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#include <stm32_ll_bus.h> |
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#include <stm32_ll_pwr.h> |
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#include <stm32_ll_rcc.h> |
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#include <stm32_ll_system.h> |
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#include <stm32_ll_utils.h> |
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#include <drivers/clock_control.h> |
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#include <sys/util.h> |
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#include <sys/__assert.h> |
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#include <drivers/clock_control/stm32_clock_control.h> |
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#include "clock_stm32_ll_common.h" |
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/* Macros to fill up prescaler values */ |
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#define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v |
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#define ahb_prescaler(v) fn_ahb_prescaler(v) |
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#define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v |
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#define apb1_prescaler(v) fn_apb1_prescaler(v) |
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#ifndef CONFIG_SOC_SERIES_STM32F0X |
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#define fn_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v |
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#define apb2_prescaler(v) fn_apb2_prescaler(v) |
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#endif /* CONFIG_SOC_SERIES_STM32F0X */ |
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#define fn_mco1_prescaler(v) LL_RCC_MCO1_DIV_ ## v |
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#define mco1_prescaler(v) fn_mco1_prescaler(v) |
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#define fn_mco2_prescaler(v) LL_RCC_MCO2_DIV_ ## v |
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#define mco2_prescaler(v) fn_mco2_prescaler(v) |
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/* Calculate MSI freq for the given range(at RUN range, not after standby) */ |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) |
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#define RCC_CALC_MSI_RUN_FREQ(range) __LL_RCC_CALC_MSI_FREQ( \ |
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range << RCC_CR_MSIRANGE_Pos) |
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#else |
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#define RCC_CALC_MSI_RUN_FREQ(range) __LL_RCC_CALC_MSI_FREQ( \ |
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LL_RCC_MSIRANGESEL_RUN, range << RCC_CR_MSIRANGE_Pos) |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32WLX) |
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#define __LL_RCC_CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) |
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#define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK4_FREQ |
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#define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHB4Prescaler |
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#elif defined(CONFIG_SOC_SERIES_STM32WLX) |
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#define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK3_FREQ |
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#define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHB3Prescaler |
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#else |
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#define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK_FREQ |
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#define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHBPrescaler |
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#endif |
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/* Identify stm32wl dual-core socs by symbol defined in CMSIS dev header file */ |
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#if (defined(CONFIG_SOC_SERIES_STM32WLX) && defined(DUAL_CORE)) |
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#define STM32WL_DUAL_CORE |
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#endif |
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/** |
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* @brief fill in AHB/APB buses configuration structure |
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*/ |
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static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init) |
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{ |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(STM32WL_DUAL_CORE) |
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clk_init->CPU2CLKDivider = ahb_prescaler(STM32_CPU2_PRESCALER); |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) |
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clk_init->CPU1CLKDivider = ahb_prescaler(STM32_CPU1_PRESCALER); |
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clk_init->AHB4CLKDivider = ahb_prescaler(STM32_AHB4_PRESCALER); |
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#elif defined(CONFIG_SOC_SERIES_STM32WLX) |
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clk_init->CPU1CLKDivider = ahb_prescaler(STM32_CPU1_PRESCALER); |
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clk_init->AHB3CLKDivider = ahb_prescaler(STM32_AHB3_PRESCALER); |
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#else |
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clk_init->AHBCLKDivider = ahb_prescaler(STM32_AHB_PRESCALER); |
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#endif /* CONFIG_SOC_SERIES_STM32WBX */ |
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clk_init->APB1CLKDivider = apb1_prescaler(STM32_APB1_PRESCALER); |
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ |
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!defined (CONFIG_SOC_SERIES_STM32G0X) |
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clk_init->APB2CLKDivider = apb2_prescaler(STM32_APB2_PRESCALER); |
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#endif |
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} |
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static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) |
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{ |
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return clock / prescaler; |
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} |
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static inline int stm32_clock_control_on(const struct device *dev, |
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clock_control_subsys_t sub_system) |
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{ |
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); |
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ARG_UNUSED(dev); |
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switch (pclken->bus) { |
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case STM32_CLOCK_BUS_AHB1: |
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LL_AHB1_GRP1_EnableClock(pclken->enr); |
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break; |
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ |
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defined(CONFIG_SOC_SERIES_STM32L5X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \ |
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defined(CONFIG_SOC_SERIES_STM32F7X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F2X) || \ |
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defined(CONFIG_SOC_SERIES_STM32WBX) || \ |
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defined(CONFIG_SOC_SERIES_STM32WLX) || \ |
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defined(CONFIG_SOC_SERIES_STM32G4X) |
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case STM32_CLOCK_BUS_AHB2: |
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LL_AHB2_GRP1_EnableClock(pclken->enr); |
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break; |
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#endif /* CONFIG_SOC_SERIES_STM32_* */ |
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ |
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defined(CONFIG_SOC_SERIES_STM32L5X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \ |
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defined(CONFIG_SOC_SERIES_STM32F7X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F2X) || \ |
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defined(CONFIG_SOC_SERIES_STM32WBX) || \ |
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defined(CONFIG_SOC_SERIES_STM32WLX) || \ |
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defined(CONFIG_SOC_SERIES_STM32G4X) |
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case STM32_CLOCK_BUS_AHB3: |
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LL_AHB3_GRP1_EnableClock(pclken->enr); |
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break; |
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#endif /* CONFIG_SOC_SERIES_STM32_* */ |
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case STM32_CLOCK_BUS_APB1: |
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LL_APB1_GRP1_EnableClock(pclken->enr); |
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break; |
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ |
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defined(CONFIG_SOC_SERIES_STM32L5X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F0X) || \ |
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defined(CONFIG_SOC_SERIES_STM32WBX) || \ |
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defined(CONFIG_SOC_SERIES_STM32WLX) || \ |
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defined(CONFIG_SOC_SERIES_STM32G4X) |
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case STM32_CLOCK_BUS_APB1_2: |
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LL_APB1_GRP2_EnableClock(pclken->enr); |
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break; |
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#endif /* CONFIG_SOC_SERIES_STM32_* */ |
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) |
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case STM32_CLOCK_BUS_APB2: |
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LL_APB2_GRP1_EnableClock(pclken->enr); |
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break; |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WLX) |
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case STM32_CLOCK_BUS_APB3: |
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LL_APB3_GRP1_EnableClock(pclken->enr); |
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break; |
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#endif |
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#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ |
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defined (CONFIG_SOC_SERIES_STM32G0X) |
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case STM32_CLOCK_BUS_IOP: |
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LL_IOP_GRP1_EnableClock(pclken->enr); |
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break; |
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#endif |
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default: |
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return -ENOTSUP; |
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} |
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return 0; |
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} |
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static inline int stm32_clock_control_off(const struct device *dev, |
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clock_control_subsys_t sub_system) |
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{ |
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); |
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ARG_UNUSED(dev); |
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switch (pclken->bus) { |
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case STM32_CLOCK_BUS_AHB1: |
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LL_AHB1_GRP1_DisableClock(pclken->enr); |
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break; |
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ |
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defined(CONFIG_SOC_SERIES_STM32L5X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \ |
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defined(CONFIG_SOC_SERIES_STM32F7X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F2X) || \ |
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defined(CONFIG_SOC_SERIES_STM32WBX) || \ |
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defined(CONFIG_SOC_SERIES_STM32WLX) || \ |
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defined(CONFIG_SOC_SERIES_STM32G4X) |
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case STM32_CLOCK_BUS_AHB2: |
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LL_AHB2_GRP1_DisableClock(pclken->enr); |
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break; |
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#endif /* CONFIG_SOC_SERIES_STM32_* */ |
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ |
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defined(CONFIG_SOC_SERIES_STM32L5X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \ |
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defined(CONFIG_SOC_SERIES_STM32F7X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F2X) || \ |
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defined(CONFIG_SOC_SERIES_STM32WBX) || \ |
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defined(CONFIG_SOC_SERIES_STM32WLX) || \ |
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defined(CONFIG_SOC_SERIES_STM32G4X) |
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case STM32_CLOCK_BUS_AHB3: |
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LL_AHB3_GRP1_DisableClock(pclken->enr); |
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break; |
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#endif /* CONFIG_SOC_SERIES_STM32_* */ |
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case STM32_CLOCK_BUS_APB1: |
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LL_APB1_GRP1_DisableClock(pclken->enr); |
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break; |
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ |
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defined(CONFIG_SOC_SERIES_STM32L5X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F0X) || \ |
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defined(CONFIG_SOC_SERIES_STM32WBX) || \ |
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defined(CONFIG_SOC_SERIES_STM32WLX) || \ |
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defined(CONFIG_SOC_SERIES_STM32G4X) |
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case STM32_CLOCK_BUS_APB1_2: |
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LL_APB1_GRP2_DisableClock(pclken->enr); |
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break; |
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#endif /* CONFIG_SOC_SERIES_STM32_* */ |
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) |
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case STM32_CLOCK_BUS_APB2: |
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LL_APB2_GRP1_DisableClock(pclken->enr); |
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break; |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WLX) |
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case STM32_CLOCK_BUS_APB3: |
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LL_APB3_GRP1_DisableClock(pclken->enr); |
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break; |
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#endif |
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#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ |
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defined (CONFIG_SOC_SERIES_STM32G0X) |
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case STM32_CLOCK_BUS_IOP: |
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LL_IOP_GRP1_DisableClock(pclken->enr); |
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break; |
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#endif |
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default: |
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return -ENOTSUP; |
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} |
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return 0; |
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} |
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static int stm32_clock_control_get_subsys_rate(const struct device *clock, |
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clock_control_subsys_t sub_system, |
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uint32_t *rate) |
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{ |
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); |
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/* |
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* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler) |
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* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC |
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* since it will be updated after clock configuration and hence |
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* more likely to contain actual clock speed |
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*/ |
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uint32_t ahb_clock = SystemCoreClock; |
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uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER); |
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ |
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!defined (CONFIG_SOC_SERIES_STM32G0X) |
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uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER); |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WLX) |
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uint32_t ahb3_clock = get_bus_clock(ahb_clock * STM32_CPU1_PRESCALER, |
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STM32_AHB3_PRESCALER); |
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#endif |
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ARG_UNUSED(clock); |
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switch (pclken->bus) { |
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case STM32_CLOCK_BUS_AHB1: |
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case STM32_CLOCK_BUS_AHB2: |
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#if !defined(CONFIG_SOC_SERIES_STM32WLX) |
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case STM32_CLOCK_BUS_AHB3: |
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#endif |
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#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ |
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defined (CONFIG_SOC_SERIES_STM32G0X) |
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case STM32_CLOCK_BUS_IOP: |
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#endif |
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*rate = ahb_clock; |
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break; |
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case STM32_CLOCK_BUS_APB1: |
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ |
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defined(CONFIG_SOC_SERIES_STM32L5X) || \ |
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defined(CONFIG_SOC_SERIES_STM32F0X) || \ |
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defined(CONFIG_SOC_SERIES_STM32WBX) || \ |
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defined(CONFIG_SOC_SERIES_STM32WLX) || \ |
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defined(CONFIG_SOC_SERIES_STM32G4X) |
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case STM32_CLOCK_BUS_APB1_2: |
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#endif /* CONFIG_SOC_SERIES_STM32_* */ |
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#if defined(CONFIG_SOC_SERIES_STM32G0X) |
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case STM32_CLOCK_BUS_APB2: |
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/* |
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* STM32G0x only has one APB, but two reset/clock enable |
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* registers for peripherals, so return the APB1 clock rate here |
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*/ |
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#endif /* CONFIG_SOC_SERIES_STM32G0X */ |
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*rate = apb1_clock; |
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break; |
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ |
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!defined (CONFIG_SOC_SERIES_STM32G0X) |
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case STM32_CLOCK_BUS_APB2: |
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*rate = apb2_clock; |
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break; |
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#endif |
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#if defined(CONFIG_SOC_SERIES_STM32WLX) |
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case STM32_CLOCK_BUS_AHB3: |
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case STM32_CLOCK_BUS_APB3: |
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/* AHB3 and APB3 share the same clock and prescaler. */ |
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*rate = ahb3_clock; |
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break; |
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#endif |
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default: |
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return -ENOTSUP; |
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} |
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return 0; |
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} |
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static struct clock_control_driver_api stm32_clock_control_api = { |
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.on = stm32_clock_control_on, |
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.off = stm32_clock_control_off, |
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.get_rate = stm32_clock_control_get_subsys_rate, |
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}; |
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/* |
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* Unconditionally switch the system clock source to HSI. |
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*/ |
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__unused |
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static void stm32_clock_switch_to_hsi(uint32_t new_ahb_prescaler) |
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{ |
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/* Enable HSI if not enabled */ |
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if (LL_RCC_HSI_IsReady() != 1) { |
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/* Enable HSI */ |
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LL_RCC_HSI_Enable(); |
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while (LL_RCC_HSI_IsReady() != 1) { |
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/* Wait for HSI ready */ |
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} |
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} |
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/* Set HSI as SYSCLCK source */ |
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); |
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LL_RCC_SetAHBPrescaler(new_ahb_prescaler); |
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) { |
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} |
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} |
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/* |
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* MCO configure doesn't active requested clock source, |
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* so please make sure the clock source was enabled. |
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*/ |
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static inline void stm32_clock_control_mco_init(void) |
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{ |
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#ifndef CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK |
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LL_RCC_ConfigMCO(MCO1_SOURCE, |
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mco1_prescaler(CONFIG_CLOCK_STM32_MCO1_DIV)); |
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#endif /* CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK */ |
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#ifndef CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK |
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LL_RCC_ConfigMCO(MCO2_SOURCE, |
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mco2_prescaler(CONFIG_CLOCK_STM32_MCO2_DIV)); |
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#endif /* CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK */ |
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} |
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/** |
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* @brief Initialize clocks for the stm32 |
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* |
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* This routine is called to enable and configure the clocks and PLL |
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* of the soc on the board. It depends on the board definition. |
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* This function is called on the startup and also to restore the config |
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* when exiting for low power mode. |
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* |
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* @param dev clock device struct |
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* |
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* @return 0 |
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*/ |
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int stm32_clock_control_init(const struct device *dev) |
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{ |
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LL_UTILS_ClkInitTypeDef s_ClkInitStruct; |
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uint32_t hclk_prescaler; |
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uint32_t flash_prescaler; |
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#if STM32_SYSCLK_SRC_HSE || STM32_SYSCLK_SRC_MSI |
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uint32_t new_hclk_freq; |
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uint32_t old_flash_freq; |
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uint32_t new_flash_freq; |
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#endif |
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ARG_UNUSED(dev); |
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/* configure clock for AHB/APB buses */ |
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config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct); |
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/* update local hclk and flash-clk prescaler variable */ |
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#if defined(CONFIG_SOC_SERIES_STM32WBX) |
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hclk_prescaler = s_ClkInitStruct.CPU1CLKDivider; |
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flash_prescaler = s_ClkInitStruct.AHB4CLKDivider; |
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#elif defined(CONFIG_SOC_SERIES_STM32WLX) |
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hclk_prescaler = s_ClkInitStruct.CPU1CLKDivider; |
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flash_prescaler = s_ClkInitStruct.AHB3CLKDivider; |
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#else |
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hclk_prescaler = s_ClkInitStruct.AHBCLKDivider; |
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flash_prescaler = hclk_prescaler; |
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#endif |
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/* Some clocks would be activated by default */ |
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config_enable_default_clocks(); |
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#if STM32_SYSCLK_SRC_PLL |
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LL_UTILS_PLLInitTypeDef s_PLLInitStruct; |
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|
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/* configure PLL input settings */ |
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config_pll_init(&s_PLLInitStruct); |
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/* |
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* Switch to HSI and disable the PLL before configuration. |
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* (Switching to HSI makes sure we have a SYSCLK source in |
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* case we're currently running from the PLL we're about to |
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* turn off and reconfigure.) |
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* |
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* Don't use s_ClkInitStruct.AHBCLKDivider as the AHB |
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* prescaler here. In this configuration, that's the value to |
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* use when the SYSCLK source is the PLL, not HSI. |
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*/ |
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stm32_clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1); |
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LL_RCC_PLL_Disable(); |
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|
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#ifdef CONFIG_SOC_SERIES_STM32F7X |
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/* Assuming we stay on Power Scale default value: Power Scale 1 */ |
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if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) { |
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LL_PWR_EnableOverDriveMode(); |
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while (LL_PWR_IsActiveFlag_OD() != 1) { |
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/* Wait for OverDrive mode ready */ |
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} |
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LL_PWR_EnableOverDriveSwitching(); |
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while (LL_PWR_IsActiveFlag_ODSW() != 1) { |
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/* Wait for OverDrive switch ready */ |
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} |
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} |
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#endif |
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#if STM32_PLL_Q_DIVISOR |
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, |
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STM32_PLL_Q_DIVISOR |
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<< RCC_PLLCFGR_PLLQ_Pos); |
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#endif /* STM32_PLL_Q_DIVISOR */ |
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#if STM32_PLL_SRC_MSI |
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|
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/* Set MSI Range */ |
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#if !defined(CONFIG_SOC_SERIES_STM32WBX) |
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LL_RCC_MSI_EnableRangeSelection(); |
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#endif |
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LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos); |
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LL_RCC_MSI_SetCalibTrimming(0); |
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|
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#if STM32_MSI_PLL_MODE |
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|
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#ifndef STM32_LSE_CLOCK |
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#error "MSI Hardware auto calibration requires LSE clock activation" |
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#endif |
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/* Enable MSI hardware auto calibration */ |
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LL_RCC_MSI_EnablePLLMode(); |
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#endif |
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|
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/* Switch to PLL with MSI as clock source */ |
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LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct); |
|
|
|
/* Disable other clocks */ |
|
LL_RCC_HSI_Disable(); |
|
LL_RCC_HSE_Disable(); |
|
|
|
#elif STM32_PLL_SRC_HSI |
|
/* Switch to PLL with HSI as clock source */ |
|
LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct); |
|
|
|
/* Disable other clocks */ |
|
LL_RCC_HSE_Disable(); |
|
LL_RCC_MSI_Disable(); |
|
|
|
#elif STM32_PLL_SRC_HSE |
|
|
|
#ifndef CONFIG_SOC_SERIES_STM32WLX |
|
int hse_bypass; |
|
if (IS_ENABLED(STM32_HSE_BYPASS)) { |
|
hse_bypass = LL_UTILS_HSEBYPASS_ON; |
|
} else { |
|
hse_bypass = LL_UTILS_HSEBYPASS_OFF; |
|
} |
|
#else |
|
if (IS_ENABLED(STM32_HSE_TCXO)) { |
|
LL_RCC_HSE_EnableTcxo(); |
|
} |
|
if (IS_ENABLED(STM32_HSE_DIV2)) { |
|
LL_RCC_HSE_EnableDiv2(); |
|
} |
|
#endif |
|
|
|
/* Switch to PLL with HSE as clock source */ |
|
LL_PLL_ConfigSystemClock_HSE( |
|
#if !defined(CONFIG_SOC_SERIES_STM32WBX) && !defined(CONFIG_SOC_SERIES_STM32WLX) |
|
CONFIG_CLOCK_STM32_HSE_CLOCK, |
|
#endif |
|
#ifndef CONFIG_SOC_SERIES_STM32WLX |
|
hse_bypass, |
|
#endif |
|
&s_PLLInitStruct, |
|
&s_ClkInitStruct); |
|
|
|
/* Disable other clocks */ |
|
LL_RCC_HSI_Disable(); |
|
LL_RCC_MSI_Disable(); |
|
|
|
#endif /* STM32_PLL_SRC_* */ |
|
|
|
#elif STM32_SYSCLK_SRC_HSE |
|
|
|
old_flash_freq = RCC_CALC_FLASH_FREQ(HAL_RCC_GetSysClockFreq(), |
|
GET_CURRENT_FLASH_PRESCALER()); |
|
|
|
/* Calculate new SystemCoreClock variable based on HSE freq */ |
|
uint32_t hse_freq; |
|
if (IS_ENABLED(STM32_HSE_DIV2)) { |
|
hse_freq = CONFIG_CLOCK_STM32_HSE_CLOCK / 2; |
|
} else { |
|
hse_freq = CONFIG_CLOCK_STM32_HSE_CLOCK; |
|
} |
|
new_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(hse_freq, hclk_prescaler); |
|
|
|
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32WLX) |
|
new_flash_freq = RCC_CALC_FLASH_FREQ(CONFIG_CLOCK_STM32_HSE_CLOCK, |
|
flash_prescaler); |
|
#else |
|
new_flash_freq = new_hclk_freq; |
|
#endif |
|
|
|
#if defined(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) |
|
__ASSERT(new_hclk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, |
|
"Config mismatch HCLK frequency %u %u", |
|
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, new_hclk_freq); |
|
#endif |
|
|
|
/* If freq increases, set flash latency before any clock setting */ |
|
if (new_flash_freq > old_flash_freq) { |
|
LL_SetFlashLatency(new_flash_freq); |
|
} |
|
|
|
/* Enable HSE if not enabled */ |
|
if (LL_RCC_HSE_IsReady() != 1) { |
|
#ifdef CONFIG_SOC_SERIES_STM32WLX |
|
if (IS_ENABLED(STM32_HSE_TCXO)) { |
|
LL_RCC_HSE_EnableTcxo(); |
|
} |
|
#elif !defined(CONFIG_SOC_SERIES_STM32WBX) |
|
/* Check if need to enable HSE bypass feature or not */ |
|
if (IS_ENABLED(STM32_HSE_BYPASS)) { |
|
LL_RCC_HSE_EnableBypass(); |
|
} else { |
|
LL_RCC_HSE_DisableBypass(); |
|
} |
|
#endif |
|
|
|
/* Enable HSE */ |
|
LL_RCC_HSE_Enable(); |
|
while (LL_RCC_HSE_IsReady() != 1) { |
|
/* Wait for HSE ready */ |
|
} |
|
} |
|
|
|
/* Set HSE as SYSCLCK source */ |
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE); |
|
LL_RCC_SetAHBPrescaler(hclk_prescaler); |
|
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) { |
|
} |
|
|
|
/* Update SystemCoreClock variable */ |
|
LL_SetSystemCoreClock(new_hclk_freq); |
|
|
|
/* Set APB1 & APB2 prescaler*/ |
|
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); |
|
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ |
|
!defined (CONFIG_SOC_SERIES_STM32G0X) |
|
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); |
|
#endif |
|
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(STM32WL_DUAL_CORE) |
|
LL_C2_RCC_SetAHBPrescaler(s_ClkInitStruct.CPU2CLKDivider); |
|
#endif |
|
#ifdef CONFIG_SOC_SERIES_STM32WBX |
|
LL_RCC_SetAHB4Prescaler(s_ClkInitStruct.AHB4CLKDivider); |
|
#endif /* CONFIG_SOC_SERIES_STM32WBX */ |
|
#ifdef CONFIG_SOC_SERIES_STM32WLX |
|
LL_RCC_SetAHB3Prescaler(s_ClkInitStruct.AHB3CLKDivider); |
|
#endif /* CONFIG_SOC_SERIES_STM32WLX */ |
|
|
|
/* If freq not increased, set flash latency after all clock setting */ |
|
if (new_flash_freq <= old_flash_freq) { |
|
LL_SetFlashLatency(new_flash_freq); |
|
} |
|
|
|
/* Disable other clocks */ |
|
LL_RCC_HSI_Disable(); |
|
LL_RCC_MSI_Disable(); |
|
LL_RCC_PLL_Disable(); |
|
|
|
#elif STM32_SYSCLK_SRC_MSI |
|
|
|
old_flash_freq = RCC_CALC_FLASH_FREQ(HAL_RCC_GetSysClockFreq(), |
|
GET_CURRENT_FLASH_PRESCALER()); |
|
|
|
new_hclk_freq = __LL_RCC_CALC_HCLK_FREQ( |
|
RCC_CALC_MSI_RUN_FREQ(STM32_MSI_RANGE), |
|
hclk_prescaler); |
|
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32WLX) |
|
new_flash_freq = RCC_CALC_FLASH_FREQ( |
|
RCC_CALC_MSI_RUN_FREQ(STM32_MSI_RANGE), |
|
flash_prescaler); |
|
#else |
|
new_flash_freq = new_hclk_freq; |
|
#endif |
|
|
|
#if defined(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) |
|
__ASSERT(new_hclk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, |
|
"Config mismatch HCLK frequency %u %u", |
|
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, new_hclk_freq); |
|
#endif |
|
|
|
/* If freq increases, set flash latency before any clock setting */ |
|
if (new_flash_freq > old_flash_freq) { |
|
LL_SetFlashLatency(new_flash_freq); |
|
} |
|
|
|
/* Set MSI Range */ |
|
#if !defined(CONFIG_SOC_SERIES_STM32WBX) |
|
LL_RCC_MSI_EnableRangeSelection(); |
|
#endif |
|
LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos); |
|
|
|
#if STM32_MSI_PLL_MODE |
|
/* Enable MSI hardware auto calibration */ |
|
LL_RCC_MSI_EnablePLLMode(); |
|
#endif |
|
|
|
/* Enable MSI if not enabled */ |
|
if (LL_RCC_MSI_IsReady() != 1) { |
|
/* Enable MSI */ |
|
LL_RCC_MSI_Enable(); |
|
while (LL_RCC_MSI_IsReady() != 1) { |
|
/* Wait for HSI ready */ |
|
} |
|
} |
|
|
|
/* Set MSI as SYSCLCK source */ |
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI); |
|
LL_RCC_SetAHBPrescaler(hclk_prescaler); |
|
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) { |
|
} |
|
|
|
/* Update SystemCoreClock variable */ |
|
LL_SetSystemCoreClock(new_hclk_freq); |
|
|
|
/* Set APB1 & APB2 prescaler*/ |
|
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); |
|
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); |
|
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(STM32WL_DUAL_CORE) |
|
LL_C2_RCC_SetAHBPrescaler(s_ClkInitStruct.CPU2CLKDivider); |
|
#endif |
|
#ifdef CONFIG_SOC_SERIES_STM32WBX |
|
LL_RCC_SetAHB4Prescaler(s_ClkInitStruct.AHB4CLKDivider); |
|
#endif |
|
#ifdef CONFIG_SOC_SERIES_STM32WLX |
|
LL_RCC_SetAHB3Prescaler(s_ClkInitStruct.AHB3CLKDivider); |
|
#endif |
|
/* If freq not increased, set flash latency after all clock setting */ |
|
if (new_flash_freq <= old_flash_freq) { |
|
LL_SetFlashLatency(new_flash_freq); |
|
} |
|
|
|
/* Disable other clocks */ |
|
LL_RCC_HSE_Disable(); |
|
LL_RCC_HSI_Disable(); |
|
LL_RCC_PLL_Disable(); |
|
|
|
#elif STM32_SYSCLK_SRC_HSI |
|
|
|
stm32_clock_switch_to_hsi(hclk_prescaler); |
|
|
|
/* Update SystemCoreClock variable */ |
|
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(HSI_VALUE, |
|
hclk_prescaler)); |
|
|
|
/* Set APB1 & APB2 prescaler*/ |
|
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); |
|
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ |
|
!defined (CONFIG_SOC_SERIES_STM32G0X) |
|
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); |
|
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ |
|
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(STM32WL_DUAL_CORE) |
|
LL_C2_RCC_SetAHBPrescaler(s_ClkInitStruct.CPU2CLKDivider); |
|
#endif |
|
#ifdef CONFIG_SOC_SERIES_STM32WBX |
|
LL_RCC_SetAHB4Prescaler(s_ClkInitStruct.AHB4CLKDivider); |
|
#endif /* CONFIG_SOC_SERIES_STM32WBX */ |
|
#ifdef CONFIG_SOC_SERIES_STM32WLX |
|
LL_RCC_SetAHB3Prescaler(s_ClkInitStruct.AHB3CLKDivider); |
|
#endif /* CONFIG_SOC_SERIES_STM32WLX */ |
|
|
|
/* Set flash latency */ |
|
/* HSI used as SYSCLK, set latency to 0 */ |
|
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); |
|
|
|
/* Disable other clocks */ |
|
LL_RCC_HSE_Disable(); |
|
LL_RCC_MSI_Disable(); |
|
LL_RCC_PLL_Disable(); |
|
|
|
#endif /* STM32_SYSCLK_SRC_... */ |
|
|
|
/* configure MCO1/MCO2 based on Kconfig */ |
|
stm32_clock_control_mco_init(); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* @brief RCC device, note that priority is intentionally set to 1 so |
|
* that the device init runs just after SOC init |
|
*/ |
|
DEVICE_DT_DEFINE(DT_NODELABEL(rcc), |
|
&stm32_clock_control_init, |
|
NULL, |
|
NULL, NULL, |
|
PRE_KERNEL_1, |
|
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, |
|
&stm32_clock_control_api);
|
|
|