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106 lines
3.4 KiB
106 lines
3.4 KiB
/* |
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* Copyright (c) 2022 Basalte bv |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT atmel_sam_smc |
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#include <zephyr/device.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/drivers/clock_control/atmel_sam_pmc.h> |
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#include <soc.h> |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(memc_sam, CONFIG_MEMC_LOG_LEVEL); |
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struct memc_smc_bank_config { |
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uint32_t cs; |
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uint32_t mode; |
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uint32_t setup_timing; |
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uint32_t pulse_timing; |
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uint32_t cycle_timing; |
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}; |
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struct memc_smc_config { |
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Smc *regs; |
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size_t banks_len; |
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const struct memc_smc_bank_config *banks; |
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const struct atmel_sam_pmc_config clock_cfg; |
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const struct pinctrl_dev_config *pcfg; |
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}; |
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static int memc_smc_init(const struct device *dev) |
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{ |
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int ret; |
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const struct memc_smc_config *cfg = dev->config; |
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SmcCs_number *bank; |
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/* Enable SMC clock in PMC */ |
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(void)clock_control_on(SAM_DT_PMC_CONTROLLER, |
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(clock_control_subsys_t)&cfg->clock_cfg); |
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); |
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if (ret < 0) { |
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return ret; |
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} |
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for (size_t i = 0U; i < cfg->banks_len; i++) { |
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if (cfg->banks[i].cs >= SMCCS_NUMBER_NUMBER) { |
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return -EINVAL; |
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} |
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bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; |
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bank->SMC_SETUP = cfg->banks[i].setup_timing; |
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bank->SMC_PULSE = cfg->banks[i].pulse_timing; |
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bank->SMC_CYCLE = cfg->banks[i].cycle_timing; |
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bank->SMC_MODE = cfg->banks[i].mode; |
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} |
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return 0; |
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} |
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#define SETUP_TIMING(node_id) \ |
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SMC_SETUP_NWE_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 0)) \ |
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| SMC_SETUP_NCS_WR_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 1)) \ |
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| SMC_SETUP_NRD_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 2)) \ |
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| SMC_SETUP_NCS_RD_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 3)) |
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#define PULSE_TIMING(node_id) \ |
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SMC_PULSE_NWE_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 0)) \ |
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| SMC_PULSE_NCS_WR_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 1)) \ |
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| SMC_PULSE_NRD_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 2)) \ |
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| SMC_PULSE_NCS_RD_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 3)) |
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#define CYCLE_TIMING(node_id) \ |
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SMC_CYCLE_NWE_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 0)) \ |
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| SMC_CYCLE_NRD_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 1)) |
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#define BANK_CONFIG(node_id) \ |
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{ \ |
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.cs = DT_REG_ADDR(node_id), \ |
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.mode = COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \ |
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(SMC_MODE_WRITE_MODE), (0)) \ |
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| COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode), \ |
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(SMC_MODE_READ_MODE), (0)), \ |
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.setup_timing = SETUP_TIMING(node_id), \ |
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.pulse_timing = PULSE_TIMING(node_id), \ |
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.cycle_timing = CYCLE_TIMING(node_id), \ |
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}, |
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#define MEMC_SMC_DEFINE(inst) \ |
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static const struct memc_smc_bank_config smc_bank_config_##inst[] = { \ |
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DT_INST_FOREACH_CHILD(inst, BANK_CONFIG) \ |
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}; \ |
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PINCTRL_DT_INST_DEFINE(inst); \ |
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static const struct memc_smc_config smc_config_##inst = { \ |
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.regs = (Smc *)DT_INST_REG_ADDR(inst), \ |
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.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(inst), \ |
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.banks_len = ARRAY_SIZE(smc_bank_config_##inst), \ |
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.banks = smc_bank_config_##inst, \ |
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ |
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}; \ |
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DEVICE_DT_INST_DEFINE(inst, memc_smc_init, NULL, NULL, \ |
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&smc_config_##inst, POST_KERNEL, \ |
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CONFIG_MEMC_INIT_PRIORITY, NULL); |
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DT_INST_FOREACH_STATUS_OKAY(MEMC_SMC_DEFINE)
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