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214 lines
4.0 KiB
214 lines
4.0 KiB
/* |
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* Copyright (c) 2023, Synopsys, Inc. All rights reserved. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include "skeleton.dtsi" |
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#include <zephyr/dt-bindings/i2c/i2c.h> |
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#include <zephyr/dt-bindings/gpio/gpio.h> |
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/ { |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "snps,archs4xd"; |
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reg = <0>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "snps,archs4xd"; |
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reg = <1>; |
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}; |
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cpu@2 { |
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device_type = "cpu"; |
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compatible = "snps,archs4xd"; |
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reg = <2>; |
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}; |
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cpu@3 { |
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device_type = "cpu"; |
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compatible = "snps,archs4xd"; |
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reg = <3>; |
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}; |
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}; |
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intc: arcv2-intc { |
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compatible = "snps,arcv2-intc"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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idu_intc: idu-interrupt-controller { |
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compatible = "snps,archs-idu-intc"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupt-parent = <&intc>; |
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}; |
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ici: intercore-interrupt-unit { |
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compatible = "snps,archs-ici"; |
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interrupts = <19 1>; |
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interrupt-parent = <&intc>; |
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}; |
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timer0: timer0 { |
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compatible = "snps,arc-timer"; |
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interrupts = <16 1>; |
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interrupt-parent = <&intc>; |
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}; |
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timer1: timer1 { |
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compatible = "snps,arc-timer"; |
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interrupts = <17 1>; |
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interrupt-parent = <&intc>; |
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}; |
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soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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interrupt-parent = <&idu_intc>; |
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ranges; |
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ddr0: memory@90000000 { |
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device_type = "memory"; |
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reg = <0x90000000 0x50000000>; |
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}; |
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uart_dbg: uart@f0005000 { |
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compatible = "ns16550"; |
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clock-frequency = <33333333>; |
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reg = <0xf0005000 0x1000>; |
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interrupts = <30 1>; |
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reg-shift = <2>; |
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}; |
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uart0: uart@f0026000 { |
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compatible = "ns16550"; |
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clock-frequency = <33333333>; |
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reg = <0xf0026000 0x100>; |
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interrupts = <46 1>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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uart1: uart@f0027000{ |
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compatible = "ns16550"; |
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clock-frequency = <33333333>; |
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reg = <0xf0027000 0x100>; |
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interrupts = <47 1>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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uart2: uart@f0028000 { |
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compatible = "ns16550"; |
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clock-frequency = <33333333>; |
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reg = <0xf0028000 0x100>; |
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interrupts = <48 1>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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gpio0: gpio@f0003000 { |
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compatible = "snps,designware-gpio"; |
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reg = <0xf0003000 0x80>; |
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ngpios = <24>; |
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interrupt-parent = <&idu_intc>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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status = "disabled"; |
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}; |
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creg_gpio: creg_gpio@f00014b0 { |
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compatible = "snps,creg-gpio"; |
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reg = <0xf00014b0 0x4>; |
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ngpios = <12>; |
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bit-per-gpio = <2>; |
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off-val = <0>; |
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on-val = <2>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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status = "disabled"; |
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}; |
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i2c0: i2c@f0023000 { |
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compatible = "snps,designware-i2c"; |
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clock-frequency = <I2C_BITRATE_STANDARD>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xf0023000 0x100>; |
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interrupts = <43 1>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@f0024000 { |
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compatible = "snps,designware-i2c"; |
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clock-frequency = <I2C_BITRATE_STANDARD>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xf0024000 0x100>; |
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interrupts = <44 1>; |
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status = "disabled"; |
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}; |
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i2c2: i2c@f0025000 { |
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compatible = "snps,designware-i2c"; |
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clock-frequency = <I2C_BITRATE_STANDARD>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xf0025000 0x100>; |
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interrupts = <45 1>; |
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status = "disabled"; |
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}; |
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spi0: spi@f0020000 { |
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compatible = "snps,designware-spi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xf0020000 0x100>; |
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interrupts = <40 1>; |
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fifo-depth = <32>; |
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max-xfer-size = <16>; |
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status = "disabled"; |
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}; |
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spi1: spi@f0021000 { |
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compatible = "snps,designware-spi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xf0021000 0x100>; |
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interrupts = <41 1>; |
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fifo-depth = <32>; |
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max-xfer-size = <16>; |
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status = "disabled"; |
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}; |
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spi2: spi@f0022000 { |
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compatible = "snps,designware-spi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xf0022000 0x100>; |
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interrupts = <42 1>; |
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fifo-depth = <32>; |
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max-xfer-size = <16>; |
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status = "disabled"; |
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}; |
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}; |
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};
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