You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
201 lines
4.3 KiB
201 lines
4.3 KiB
/* |
|
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space) |
|
* |
|
* SPDX-License-Identifier: Apache-2.0 |
|
*/ |
|
|
|
#include <freq.h> |
|
#include <mem.h> |
|
#include <wch/qingke-v4c.dtsi> |
|
#include <zephyr/dt-bindings/gpio/gpio.h> |
|
#include <zephyr/dt-bindings/i2c/i2c.h> |
|
#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h> |
|
|
|
/ { |
|
clocks { |
|
clk_hse: clk-hse { |
|
#clock-cells = <0>; |
|
compatible = "wch,ch32v00x-hse-clock"; |
|
clock-frequency = <DT_FREQ_M(32)>; |
|
status = "disabled"; |
|
}; |
|
|
|
clk_hsi: clk-hsi { |
|
#clock-cells = <0>; |
|
compatible = "wch,ch32v00x-hsi-clock"; |
|
clock-frequency = <DT_FREQ_M(8)>; |
|
status = "disabled"; |
|
}; |
|
|
|
clk_lsi: clk-lsi { |
|
#clock-cells = <0>; |
|
compatible = "fixed-clock"; |
|
clock-frequency = <DT_FREQ_K(32)>; |
|
status = "disabled"; |
|
}; |
|
|
|
pll: pll { |
|
#clock-cells = <0>; |
|
compatible = "wch,ch32v20x_30x-pll-clock"; |
|
mul = <15>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
soc { |
|
sram0: memory@20000000 { |
|
compatible = "mmio-sram"; |
|
reg = <0x20000000 DT_SIZE_K(64)>; |
|
}; |
|
|
|
flash: flash-controller@40022000 { |
|
compatible = "wch,ch32v20x_30x-flash-controller"; |
|
reg = <0x40022000 0x400>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
|
|
flash0: flash@8000000 { |
|
compatible = "soc-nv-flash"; |
|
reg = <0x08000000 DT_SIZE_K(480)>; |
|
}; |
|
}; |
|
|
|
pwr: pwr@40007000 { |
|
compatible = "wch,pwr"; |
|
reg = <0x40007000 16>; |
|
}; |
|
|
|
iwdg: watchdog@40003000 { |
|
compatible = "wch,iwdg"; |
|
reg = <0x40003000 0x10>; |
|
status = "disabled"; |
|
}; |
|
|
|
exti: interrupt-controller@40010400 { |
|
compatible = "wch,exti"; |
|
interrupt-controller; |
|
#interrupt-cells = <1>; |
|
reg = <0x40010400 16>; |
|
interrupt-parent = <&pfic>; |
|
num-lines = <16>; |
|
line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, <4 1>, |
|
<5 5>, <10 6>; |
|
interrupts = <22 23 24 25 26 39 56>; |
|
interrupt-names = "line0", "line1", "line2", "line3", |
|
"line4", "line5-9", "line10-15"; |
|
status = "disabled"; |
|
}; |
|
|
|
pinctrl: pin-controller@40010000 { |
|
compatible = "wch,20x_30x-afio"; |
|
reg = <0x40010000 16>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>; |
|
|
|
gpioa: gpio@40010800 { |
|
compatible = "wch,gpio"; |
|
reg = <0x40010800 0x20>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
ngpios = <16>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>; |
|
}; |
|
|
|
gpiob: gpio@40010C00 { |
|
compatible = "wch,gpio"; |
|
reg = <0x40010C00 0x20>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
ngpios = <16>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>; |
|
}; |
|
|
|
gpioc: gpio@40011000 { |
|
compatible = "wch,gpio"; |
|
reg = <0x40011000 0x20>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
ngpios = <16>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>; |
|
}; |
|
|
|
gpiod: gpio@40011400 { |
|
compatible = "wch,gpio"; |
|
reg = <0x40011400 0x20>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
ngpios = <16>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>; |
|
}; |
|
}; |
|
|
|
usart1: uart@40013800 { |
|
compatible = "wch,usart"; |
|
reg = <0x40013800 0x20>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>; |
|
interrupt-parent = <&pfic>; |
|
interrupts = <53>; |
|
status = "disabled"; |
|
}; |
|
|
|
usart2: uart@40004400 { |
|
compatible = "wch,usart"; |
|
reg = <0x40004400 0x20>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>; |
|
interrupt-parent = <&pfic>; |
|
interrupts = <54>; |
|
status = "disabled"; |
|
}; |
|
|
|
usart3: uart@40004800 { |
|
compatible = "wch,usart"; |
|
reg = <0x40004800 0x20>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>; |
|
interrupt-parent = <&pfic>; |
|
interrupts = <55>; |
|
status = "disabled"; |
|
}; |
|
|
|
usart4: uart@40004c00 { |
|
compatible = "wch,usart"; |
|
reg = <0x40004C00 0x20>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>; |
|
interrupt-parent = <&pfic>; |
|
interrupts = <68>; |
|
status = "disabled"; |
|
}; |
|
|
|
spi1: spi@40013000 { |
|
compatible = "wch,spi"; |
|
reg = <0x40013000 0x24>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_SPI1>; |
|
interrupt-parent = <&pfic>; |
|
interrupts = <51>; |
|
status = "disabled"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
}; |
|
|
|
spi2: spi@40003800 { |
|
compatible = "wch,spi"; |
|
reg = <0x40003800 0x24>; |
|
clocks = <&rcc CH32V20X_V30X_CLOCK_SPI2>; |
|
interrupt-parent = <&pfic>; |
|
interrupts = <52>; |
|
status = "disabled"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
}; |
|
|
|
rcc: rcc@40021000 { |
|
compatible = "wch,rcc"; |
|
reg = <0x40021000 16>; |
|
#clock-cells = <1>; |
|
}; |
|
}; |
|
}; |
|
|
|
&cpu0 { |
|
clock-frequency = <DT_FREQ_M(120)>; |
|
};
|
|
|