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228 lines
6.4 KiB
228 lines
6.4 KiB
/* |
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* Copyright (c) 2018 Foundries.io |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT openisa_rv32m1_intmux |
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/** |
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* @file |
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* @brief RV32M1 INTMUX (interrupt multiplexer) driver |
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* |
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* This driver provides support for level 2 interrupts on the RV32M1 |
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* SoC using the INTMUX peripheral. |
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* |
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* Each of the RI5CY and ZERO-RISCY cores has an INTMUX peripheral; |
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* INTMUX0 is wired to the RI5CY event unit interrupt table, while |
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* INTMUX1 is used with ZERO-RISCY. |
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* |
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* For this reason, only a single intmux device is declared here. The |
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* dtsi for each core needs to set up the intmux device and any |
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* associated IRQ numbers to work with this driver. |
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*/ |
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#include <zephyr/kernel.h> |
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#include <zephyr/devicetree/interrupt_controller.h> |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/init.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/irq_nextlevel.h> |
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#include <zephyr/sw_isr_table.h> |
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#include <soc.h> |
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#include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h> |
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/* |
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* CHn_VEC registers are offset by a value that is convenient if |
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* you're dealing with a Cortex-M NVIC vector table; we're not, so it |
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* needs to be subtracted out to get a useful value. |
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*/ |
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#define VECN_OFFSET 48U |
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struct rv32m1_intmux_config { |
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INTMUX_Type *regs; |
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const struct device *clock_dev; |
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clock_control_subsys_t clock_subsys; |
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const struct _isr_table_entry *isr_base; |
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}; |
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#define DEV_REGS(dev) (((const struct rv32m1_intmux_config *)(dev->config))->regs) |
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/* |
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* <irq_nextlevel.h> API |
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*/ |
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static void rv32m1_intmux_irq_enable(const struct device *dev, uint32_t irq) |
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{ |
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INTMUX_Type *regs = DEV_REGS(dev); |
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uint32_t channel = rv32m1_intmux_channel(irq); |
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uint32_t line = rv32m1_intmux_line(irq); |
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regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line); |
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} |
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static void rv32m1_intmux_irq_disable(const struct device *dev, uint32_t irq) |
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{ |
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INTMUX_Type *regs = DEV_REGS(dev); |
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uint32_t channel = rv32m1_intmux_channel(irq); |
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uint32_t line = rv32m1_intmux_line(irq); |
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regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line); |
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} |
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static uint32_t rv32m1_intmux_get_state(const struct device *dev) |
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{ |
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INTMUX_Type *regs = DEV_REGS(dev); |
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size_t i; |
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for (i = 0; i < INTMUX_CHn_IER_31_0_COUNT; i++) { |
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if (regs->CHANNEL[i].CHn_IER_31_0) { |
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return 1; |
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} |
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} |
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return 0; |
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} |
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static int rv32m1_intmux_get_line_state(const struct device *dev, |
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unsigned int irq) |
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{ |
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INTMUX_Type *regs = DEV_REGS(dev); |
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uint32_t channel = rv32m1_intmux_channel(irq); |
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uint32_t line = rv32m1_intmux_line(irq); |
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if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) { |
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return 1; |
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} |
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return 0; |
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} |
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/* |
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* IRQ handling. |
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*/ |
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#define ISR_ENTRY(channel, line) \ |
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((channel) * CONFIG_MAX_IRQ_PER_AGGREGATOR + line) |
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static void rv32m1_intmux_isr(const void *arg) |
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{ |
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const struct device *const dev = DEVICE_DT_INST_GET(0); |
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const struct rv32m1_intmux_config *config = dev->config; |
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INTMUX_Type *regs = DEV_REGS(dev); |
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uint32_t channel = POINTER_TO_UINT(arg); |
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uint32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2); |
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const struct _isr_table_entry *isr_base = config->isr_base; |
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const struct _isr_table_entry *entry; |
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/* |
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* Make sure the vector is valid, there is a note of page 1243~1244 |
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* of chapter 36 INTMUX of RV32M1 RM, |
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* Note: Unlike the NVIC, the INTMUX does not latch pending source |
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* interrupts. This means that the INTMUX output channel ISRs must |
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* check for and handle a 0 value of the CHn_VEC register to |
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* account for spurious interrupts. |
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*/ |
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if (line < VECN_OFFSET) { |
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return; |
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} |
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entry = &isr_base[ISR_ENTRY(channel, (line - VECN_OFFSET))]; |
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entry->isr(entry->arg); |
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} |
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/* |
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* Instance and initialization |
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*/ |
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static const struct irq_next_level_api rv32m1_intmux_apis = { |
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.intr_enable = rv32m1_intmux_irq_enable, |
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.intr_disable = rv32m1_intmux_irq_disable, |
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.intr_get_state = rv32m1_intmux_get_state, |
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.intr_get_line_state = rv32m1_intmux_get_line_state, |
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}; |
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static const struct rv32m1_intmux_config rv32m1_intmux_cfg = { |
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.regs = (INTMUX_Type *)DT_INST_REG_ADDR(0), |
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)), |
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.clock_subsys = UINT_TO_POINTER(DT_INST_CLOCKS_CELL(0, name)), |
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.isr_base = &_sw_isr_table[CONFIG_2ND_LVL_ISR_TBL_OFFSET], |
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}; |
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static int rv32m1_intmux_init(const struct device *dev) |
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{ |
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const struct rv32m1_intmux_config *config = dev->config; |
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INTMUX_Type *regs = DEV_REGS(dev); |
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size_t i; |
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if (!device_is_ready(config->clock_dev)) { |
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return -ENODEV; |
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} |
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/* Enable INTMUX clock. */ |
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clock_control_on(config->clock_dev, config->clock_subsys); |
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/* |
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* Reset all channels, not just the ones we're configured to |
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* support. We don't want to continue to take level 2 IRQs |
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* enabled by bootloaders, for example. |
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*/ |
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for (i = 0; i < INTMUX_CHn_CSR_COUNT; i++) { |
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regs->CHANNEL[i].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK; |
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} |
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/* Connect and enable level 1 (channel) interrupts. */ |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_0 |
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IRQ_CONNECT(INTMUX_CH0_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(0), 0); |
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irq_enable(INTMUX_CH0_IRQ); |
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#endif |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_1 |
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IRQ_CONNECT(INTMUX_CH1_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(1), 0); |
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irq_enable(INTMUX_CH1_IRQ); |
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#endif |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_2 |
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IRQ_CONNECT(INTMUX_CH2_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(2), 0); |
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irq_enable(INTMUX_CH2_IRQ); |
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#endif |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_3 |
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IRQ_CONNECT(INTMUX_CH3_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(3), 0); |
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irq_enable(INTMUX_CH3_IRQ); |
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#endif |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_4 |
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IRQ_CONNECT(INTMUX_CH4_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(4), 0); |
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irq_enable(INTMUX_CH4_IRQ); |
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#endif |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_5 |
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IRQ_CONNECT(INTMUX_CH5_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(5), 0); |
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irq_enable(INTMUX_CH5_IRQ); |
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#endif |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_6 |
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IRQ_CONNECT(INTMUX_CH6_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(6), 0); |
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irq_enable(INTMUX_CH6_IRQ); |
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#endif |
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#ifdef CONFIG_RV32M1_INTMUX_CHANNEL_7 |
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IRQ_CONNECT(INTMUX_CH7_IRQ, 0, rv32m1_intmux_isr, |
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UINT_TO_POINTER(7), 0); |
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irq_enable(INTMUX_CH7_IRQ); |
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#endif |
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return 0; |
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} |
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DEVICE_DT_INST_DEFINE(0, &rv32m1_intmux_init, NULL, NULL, |
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&rv32m1_intmux_cfg, PRE_KERNEL_1, |
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CONFIG_RV32M1_INTMUX_INIT_PRIORITY, &rv32m1_intmux_apis); |
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#define INTC_CHILD_IRQ_ENTRY_DEF(node_id) \ |
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IRQ_PARENT_ENTRY_DEFINE(CONCAT(DT_DRV_COMPAT, _child_, DT_NODE_CHILD_IDX(node_id)), NULL, \ |
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DT_IRQN(node_id), INTC_CHILD_ISR_TBL_OFFSET(node_id), \ |
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DT_INTC_GET_AGGREGATOR_LEVEL(node_id)); |
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DT_INST_FOREACH_CHILD_STATUS_OKAY(0, INTC_CHILD_IRQ_ENTRY_DEF);
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