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439 lines
15 KiB
439 lines
15 KiB
/* |
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* Copyright (c) 2024 Silicon Laboratories Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT silabs_siwx91x_gpio |
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#include "sl_si91x_driver_gpio.h" |
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#include "sl_status.h" |
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#include <errno.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/pm/device.h> |
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#include <zephyr/pm/device_runtime.h> |
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/* Zephyr GPIO header must be included after driver, due to symbol conflicts |
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* for GPIO_INPUT and GPIO_OUTPUT between preprocessor macros in the Zephyr |
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* API and struct member register definitions for the SiWx91x device. |
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*/ |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#if CONFIG_GPIO_SILABS_SIWX91X_COMMON_INIT_PRIORITY >= CONFIG_GPIO_INIT_PRIORITY |
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#error CONFIG_GPIO_SILABS_SIWX91X_COMMON_INIT_PRIORITY must be less than \ |
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CONFIG_GPIO_INIT_PRIORITY. |
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#endif |
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#define MAX_PORT_COUNT 4 |
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#define MAX_PIN_COUNT 16 |
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#define INVALID_PORT 0xFF |
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#define INTERRUPT_COUNT 8 |
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/* Types */ |
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struct gpio_siwx91x_common_config { |
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EGPIO_Type *reg; |
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}; |
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struct gpio_siwx91x_port_config { |
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/* gpio_driver_config needs to be first */ |
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struct gpio_driver_config common; |
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const struct device *parent; |
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uint8_t pads[MAX_PIN_COUNT]; |
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int port; |
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int hal_port; |
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bool ulp; |
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}; |
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struct gpio_siwx91x_common_data { |
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/* a list of all ports */ |
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const struct device *ports[MAX_PORT_COUNT]; |
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sl_gpio_t interrupts[INTERRUPT_COUNT]; |
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}; |
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struct gpio_siwx91x_port_data { |
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/* gpio_driver_data needs to be first */ |
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struct gpio_driver_data common; |
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/* port ISR callback routine address */ |
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sys_slist_t callbacks; |
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#if defined(CONFIG_PM) |
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/* stores the direction of each pin */ |
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uint16_t pin_direction[MAX_PIN_COUNT]; |
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#endif |
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}; |
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/* Functions */ |
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static int gpio_siwx91x_port_pm_action(const struct device *port, enum pm_device_action action) |
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{ |
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__maybe_unused const struct gpio_siwx91x_port_config *config = port->config; |
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__maybe_unused struct gpio_siwx91x_port_data *data = port->data; |
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#if defined(CONFIG_PM) |
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switch (action) { |
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case PM_DEVICE_ACTION_RESUME: |
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for (int pin = 0; pin < MAX_PIN_COUNT; ++pin) { |
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if (config->common.port_pin_mask & BIT(pin)) { |
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sl_si91x_gpio_set_pin_direction(config->hal_port, pin, |
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data->pin_direction[pin]); |
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} |
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} |
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break; |
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case PM_DEVICE_ACTION_SUSPEND: |
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for (int pin = 0; pin < MAX_PIN_COUNT; ++pin) { |
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if (config->common.port_pin_mask & BIT(pin)) { |
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data->pin_direction[pin] = |
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sl_si91x_gpio_get_pin_direction(config->hal_port, pin); |
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} |
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} |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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#endif |
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return 0; |
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} |
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static int gpio_siwx91x_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = dev->config; |
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const struct device *parent = cfg->parent; |
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const struct gpio_siwx91x_common_config *pcfg = parent->config; |
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sl_status_t status; |
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sl_si91x_gpio_driver_disable_state_t disable_state = GPIO_HZ; |
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if (flags & GPIO_SINGLE_ENDED) { |
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return -ENOTSUP; |
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} |
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uint8_t pad = cfg->pads[pin]; |
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if (pad == 0) { |
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/* Enable MCU pad */ |
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status = sl_si91x_gpio_driver_enable_host_pad_selection((cfg->hal_port << 4) | pin); |
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if (status != SL_STATUS_OK) { |
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return -ENODEV; |
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} |
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} else if (pad != 0xFF && pad != 9) { |
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/* Assign pad to MCU subsystem */ |
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status = sl_si91x_gpio_driver_enable_pad_selection(pad); |
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if (status != SL_STATUS_OK) { |
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return -ENODEV; |
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} |
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} |
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if (flags & GPIO_PULL_UP) { |
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disable_state = GPIO_PULLUP; |
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} else if (flags & GPIO_PULL_DOWN) { |
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disable_state = GPIO_PULLDOWN; |
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} |
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if (cfg->ulp) { |
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sl_si91x_gpio_select_ulp_pad_driver_disable_state(pin, disable_state); |
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} else { |
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sl_si91x_gpio_select_pad_driver_disable_state((cfg->port << 4) | pin, |
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disable_state); |
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} |
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if (flags & GPIO_INPUT) { |
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if (cfg->ulp) { |
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sl_si91x_gpio_driver_enable_ulp_pad_receiver(pin); |
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} else { |
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sl_si91x_gpio_driver_enable_pad_receiver((cfg->port << 4) | pin); |
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} |
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} else { |
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if (cfg->ulp) { |
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sl_si91x_gpio_driver_disable_ulp_pad_receiver(pin); |
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} else { |
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sl_si91x_gpio_driver_disable_pad_receiver((cfg->port << 4) | pin); |
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} |
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} |
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pcfg->reg->PIN_CONFIG[(cfg->port << 4) + pin].GPIO_CONFIG_REG_b.MODE = 0; |
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if (flags & GPIO_OUTPUT_INIT_HIGH) { |
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sl_gpio_set_pin_output(cfg->hal_port, pin); |
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} else if (flags & GPIO_OUTPUT_INIT_LOW) { |
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sl_gpio_clear_pin_output(cfg->hal_port, pin); |
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} |
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sl_si91x_gpio_set_pin_direction(cfg->hal_port, pin, (flags & GPIO_OUTPUT) ? 0 : 1); |
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return 0; |
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} |
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static int gpio_siwx91x_port_get(const struct device *port, gpio_port_value_t *value) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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*value = sl_gpio_get_port_input(cfg->hal_port); |
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return 0; |
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} |
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static int gpio_siwx91x_port_set_masked(const struct device *port, gpio_port_pins_t mask, |
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gpio_port_value_t value) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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const struct device *parent = cfg->parent; |
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const struct gpio_siwx91x_common_config *pcfg = parent->config; |
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/* Cannot use HAL function sl_gpio_set_port_output_value(), as it doesn't clear bits. */ |
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pcfg->reg->PORT_CONFIG[cfg->port].PORT_LOAD_REG = |
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(pcfg->reg->PORT_CONFIG[cfg->port].PORT_LOAD_REG & ~mask) | (value & mask); |
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return 0; |
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} |
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static int gpio_siwx91x_port_set_bits(const struct device *port, gpio_port_pins_t pins) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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sl_gpio_set_port_output(cfg->hal_port, pins); |
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return 0; |
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} |
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static int gpio_siwx91x_port_clear_bits(const struct device *port, gpio_port_pins_t pins) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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sl_gpio_clear_port_output(cfg->hal_port, pins); |
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return 0; |
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} |
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static int gpio_siwx91x_port_toggle_bits(const struct device *port, gpio_port_pins_t pins) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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sl_gpio_toggle_port_output(cfg->hal_port, pins); |
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return 0; |
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} |
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static bool receiver_enabled(bool ulp, sl_gpio_port_t port, int pin) |
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{ |
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if (ulp) { |
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return ULP_PAD_CONFIG_REG & BIT(pin); |
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} else { |
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return PAD_REG(((port << 4) | pin))->GPIO_PAD_CONFIG_REG_b.PADCONFIG_REN; |
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} |
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} |
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int gpio_siwx91x_port_get_direction(const struct device *port, gpio_port_pins_t map, |
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gpio_port_pins_t *inputs, gpio_port_pins_t *outputs) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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if (inputs != NULL) { |
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*inputs = 0; |
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} |
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if (outputs != NULL) { |
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*outputs = 0; |
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} |
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for (int i = 0; i < MAX_PIN_COUNT; i++) { |
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if ((map & BIT(i))) { |
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if (sl_si91x_gpio_get_pin_direction(cfg->hal_port, i) == 0) { |
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if (outputs != NULL) { |
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*outputs |= BIT(i); |
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} |
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} |
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if (receiver_enabled(cfg->ulp, cfg->port, i)) { |
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if (inputs != NULL) { |
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*inputs |= BIT(i); |
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} |
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} |
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} |
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} |
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return 0; |
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} |
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static int gpio_siwx91x_manage_callback(const struct device *port, struct gpio_callback *callback, |
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bool set) |
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{ |
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struct gpio_siwx91x_port_data *data = port->data; |
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return gpio_manage_callback(&data->callbacks, callback, set); |
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} |
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static int gpio_siwx91x_interrupt_configure(const struct device *port, gpio_pin_t pin, |
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enum gpio_int_mode mode, enum gpio_int_trig trig) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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const struct device *parent = cfg->parent; |
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const struct gpio_siwx91x_common_config *pcfg = parent->config; |
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struct gpio_siwx91x_common_data *data = parent->data; |
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sl_si91x_gpio_interrupt_config_flag_t flags = 0; |
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if (mode & GPIO_INT_DISABLE) { |
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ARRAY_FOR_EACH(data->interrupts, i) { |
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if (data->interrupts[i].port == cfg->port && |
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data->interrupts[i].pin == pin) { |
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data->interrupts[i].port = INVALID_PORT; |
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if (cfg->ulp) { |
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sl_si91x_gpio_configure_ulp_pin_interrupt(i, flags, pin); |
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} else { |
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sl_gpio_configure_interrupt(cfg->port, pin, i, flags); |
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} |
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/* Configure function doesn't mask interrupts when disabling */ |
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pcfg->reg->INTR[i].GPIO_INTR_CTRL_b.MASK = 1; |
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if (cfg->ulp) { |
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sl_si91x_gpio_clear_ulp_interrupt(i); |
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} else { |
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sl_gpio_clear_interrupts(i); |
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} |
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return 0; |
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} |
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} |
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/* No interrupt to disable, but this is not an error */ |
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return 0; |
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} |
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if (trig == GPIO_INT_TRIG_LOW) { |
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flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_FALL_EDGE |
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: SL_GPIO_INTERRUPT_LEVEL_LOW; |
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} else if (trig == GPIO_INT_TRIG_HIGH) { |
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flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_RISE_EDGE |
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: SL_GPIO_INTERRUPT_LEVEL_HIGH; |
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} else if (trig == GPIO_INT_TRIG_BOTH) { |
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/* SL_GPIO_INTERRUPT_RISE_FALL_EDGE would make more sense, but HAL |
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* implementation is buggy. |
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*/ |
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flags = SL_GPIO_INTERRUPT_RISE_EDGE | SL_GPIO_INTERRUPT_FALL_EDGE; |
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} |
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ARRAY_FOR_EACH(data->interrupts, i) { |
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if (data->interrupts[i].port == INVALID_PORT || |
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(data->interrupts[i].port == cfg->port && data->interrupts[i].pin == pin)) { |
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data->interrupts[i].port = cfg->port; |
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data->interrupts[i].pin = pin; |
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if (cfg->ulp) { |
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sl_si91x_gpio_configure_ulp_pin_interrupt(i, flags, pin); |
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} else { |
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sl_gpio_configure_interrupt(cfg->port, pin, i, flags); |
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} |
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return 0; |
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} |
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} |
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/* No more available interrupts */ |
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return -EBUSY; |
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} |
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static inline int gpio_siwx91x_init_port(const struct device *port) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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const struct device *parent = cfg->parent; |
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struct gpio_siwx91x_common_data *data = parent->data; |
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/* Register port as active */ |
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__ASSERT(cfg->port < MAX_PORT_COUNT, "Too many ports"); |
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data->ports[cfg->port] = port; |
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return pm_device_driver_init(port, gpio_siwx91x_port_pm_action); |
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} |
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static void gpio_siwx91x_isr(const struct device *parent) |
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{ |
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const struct gpio_siwx91x_common_config *pcfg = parent->config; |
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struct gpio_siwx91x_common_data *common = parent->data; |
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const struct device *port; |
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struct gpio_siwx91x_port_data *data; |
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ARRAY_FOR_EACH(common->interrupts, i) { |
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sl_gpio_port_t port_no = common->interrupts[i].port; |
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uint32_t pending = pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS; |
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if (pending && port_no != INVALID_PORT) { |
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/* Clear interrupt */ |
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pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS = 1; |
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port = common->ports[port_no]; |
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data = port->data; |
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gpio_fire_callbacks(&data->callbacks, port, BIT(common->interrupts[i].pin)); |
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} |
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} |
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} |
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static uint32_t gpio_siwx91x_get_pending_int(const struct device *port) |
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{ |
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const struct gpio_siwx91x_port_config *cfg = port->config; |
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const struct device *parent = cfg->parent; |
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const struct gpio_siwx91x_common_config *pcfg = parent->config; |
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uint32_t status = 0; |
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ARRAY_FOR_EACH(pcfg->reg->INTR, i) { |
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if (pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS) { |
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status |= BIT(i); |
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} |
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} |
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return status; |
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} |
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static DEVICE_API(gpio, gpio_siwx91x_api) = { |
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.pin_configure = gpio_siwx91x_pin_configure, |
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.port_get_raw = gpio_siwx91x_port_get, |
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.port_set_masked_raw = gpio_siwx91x_port_set_masked, |
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.port_set_bits_raw = gpio_siwx91x_port_set_bits, |
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.port_clear_bits_raw = gpio_siwx91x_port_clear_bits, |
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.port_toggle_bits = gpio_siwx91x_port_toggle_bits, |
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.pin_interrupt_configure = gpio_siwx91x_interrupt_configure, |
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.manage_callback = gpio_siwx91x_manage_callback, |
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.get_pending_int = gpio_siwx91x_get_pending_int, |
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#ifdef CONFIG_GPIO_GET_DIRECTION |
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.port_get_direction = gpio_siwx91x_port_get_direction, |
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#endif |
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}; |
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#define GPIO_PORT_INIT(n) \ |
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static const struct gpio_siwx91x_port_config gpio_siwx91x_port_config##n = { \ |
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.common.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(n), \ |
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.parent = DEVICE_DT_GET(DT_PARENT(n)), \ |
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.pads = DT_PROP(n, silabs_pads), \ |
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.port = DT_REG_ADDR(n), \ |
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.hal_port = (DT_PROP(DT_PARENT(n), silabs_ulp) ? SL_GPIO_ULP_PORT : 0) + \ |
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DT_REG_ADDR(n), \ |
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.ulp = DT_PROP(DT_PARENT(n), silabs_ulp), \ |
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}; \ |
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static struct gpio_siwx91x_port_data gpio_siwx91x_port_data##n; \ |
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\ |
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PM_DEVICE_DT_INST_DEFINE(n, gpio_siwx91x_port_pm_action); \ |
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DEVICE_DT_DEFINE(n, gpio_siwx91x_init_port, PM_DEVICE_DT_INST_GET(n), \ |
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&gpio_siwx91x_port_data##n, &gpio_siwx91x_port_config##n, PRE_KERNEL_1, \ |
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CONFIG_GPIO_INIT_PRIORITY, &gpio_siwx91x_api); |
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#define CONFIGURE_SHARED_INTERRUPT(node_id, prop, idx) \ |
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IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), DT_IRQ_BY_IDX(node_id, idx, priority), \ |
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gpio_siwx91x_isr, DEVICE_DT_GET(node_id), 0); \ |
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irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq)); |
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static DEVICE_API(gpio, gpio_siwx91x_common_api) = { }; |
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#define GPIO_CONTROLLER_INIT(idx) \ |
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static const struct gpio_siwx91x_common_config gpio_siwx91x_config##idx = { \ |
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.reg = (EGPIO_Type *)DT_INST_REG_ADDR(idx), \ |
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}; \ |
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static struct gpio_siwx91x_common_data gpio_siwx91x_data##idx; \ |
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\ |
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static int gpio_siwx91x_init_controller_##idx(const struct device *dev) \ |
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{ \ |
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struct gpio_siwx91x_common_data *data = dev->data; \ |
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int status; \ |
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\ |
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status = sl_si91x_gpio_driver_enable_clock( \ |
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COND_CODE_1(DT_INST_PROP(idx, silabs_ulp), (ULPCLK_GPIO), (M4CLK_GPIO))); \ |
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if (status) { \ |
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return -ENODEV; \ |
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} \ |
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ARRAY_FOR_EACH(data->interrupts, i) { \ |
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data->interrupts[i].port = INVALID_PORT; \ |
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} \ |
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DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, CONFIGURE_SHARED_INTERRUPT); \ |
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return 0; \ |
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} \ |
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DEVICE_DT_INST_DEFINE(idx, gpio_siwx91x_init_controller_##idx, NULL, \ |
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&gpio_siwx91x_data##idx, &gpio_siwx91x_config##idx, \ |
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PRE_KERNEL_1, CONFIG_GPIO_SILABS_SIWX91X_COMMON_INIT_PRIORITY, \ |
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&gpio_siwx91x_common_api); \ |
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DT_INST_FOREACH_CHILD_STATUS_OKAY(idx, GPIO_PORT_INIT); |
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DT_INST_FOREACH_STATUS_OKAY(GPIO_CONTROLLER_INIT)
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