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222 lines
7.0 KiB
222 lines
7.0 KiB
/* |
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* Copyright (c) 2024 Junho Lee <junho@tsnlab.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT raspberrypi_rp1_gpio |
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#include <zephyr/arch/common/sys_bitops.h> |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/device.h> |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#define GPIO_STATUS(base, n) (base + 0x8 * n) |
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#define GPIO_CTRL(base, n) (GPIO_STATUS(base, n) + 0x4) |
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#define GPIO_STATUS_OUT_TO_PAD 0x200 |
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#define GPIO_STATUS_OUT_FROM_PERI 0x100 |
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#define GPIO_CTRL_OUTOVER_MASK 0x3000 |
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#define GPIO_CTRL_OUTOVER_PERI 0x0 |
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#define GPIO_CTRL_OEOVER_MASK 0xc000 |
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#define GPIO_CTRL_OEOVER_PERI 0x0 |
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#define GPIO_CTRL_FUNCSEL_MASK 0x001f |
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#define GPIO_CTRL_FUNCSEL_RIO 0x5 |
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#define RIO_OUT(base) (base) |
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#define RIO_OE(base) (base + 0x4) |
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#define RIO_IN(base) (base + 0x8) |
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#define RIO_SET 0x2000 |
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#define RIO_CLR 0x3000 |
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#define RIO_OUT_SET(base) (RIO_OUT(base) + RIO_SET) |
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#define RIO_OUT_CLR(base) (RIO_OUT(base) + RIO_CLR) |
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#define RIO_OE_SET(base) (RIO_OE(base) + RIO_SET) |
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#define RIO_OE_CLR(base) (RIO_OE(base) + RIO_CLR) |
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#define PADS_CTRL(base, n) (base + 0x4 * (n + 1)) |
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#define PADS_OUTPUT_DISABLE 0x80 |
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#define PADS_INPUT_ENABLE 0x40 |
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#define PADS_PULL_UP_ENABLE 0x8 |
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#define PADS_PULL_DOWN_ENABLE 0x4 |
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#define DEV_CFG(dev) ((const struct gpio_rp1_config *)(dev)->config) |
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#define DEV_DATA(dev) ((struct gpio_rp1_data *)(dev)->data) |
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struct gpio_rp1_config { |
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struct gpio_driver_config common; |
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DEVICE_MMIO_NAMED_ROM(reg_base); |
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mem_addr_t gpio_offset; |
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mem_addr_t rio_offset; |
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mem_addr_t pads_offset; |
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uint8_t ngpios; |
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}; |
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struct gpio_rp1_data { |
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struct gpio_driver_data common; |
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DEVICE_MMIO_NAMED_RAM(reg_base); |
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mem_addr_t gpio_base; |
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mem_addr_t rio_base; |
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mem_addr_t pads_base; |
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}; |
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static int gpio_rp1_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags) |
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{ |
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struct gpio_rp1_data *data = port->data; |
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if (flags & GPIO_SINGLE_ENDED) { |
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return -ENOTSUP; |
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} |
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/* Let RIO handle the input/output of GPIO */ |
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sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OEOVER_MASK); |
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sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OEOVER_PERI); |
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sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OUTOVER_MASK); |
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sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OUTOVER_PERI); |
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sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_FUNCSEL_MASK); |
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sys_set_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_FUNCSEL_RIO); |
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/* Set the direction */ |
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if (flags & GPIO_OUTPUT) { |
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sys_set_bit(RIO_OE_SET(data->rio_base), pin); |
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sys_clear_bits(PADS_CTRL(data->pads_base, pin), |
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PADS_OUTPUT_DISABLE | PADS_INPUT_ENABLE); |
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if (flags & GPIO_OUTPUT_INIT_HIGH) { |
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sys_set_bit(RIO_OUT_SET(data->rio_base), pin); |
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sys_clear_bit(RIO_OUT_CLR(data->rio_base), pin); |
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} else if (flags & GPIO_OUTPUT_INIT_LOW) { |
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sys_set_bit(RIO_OUT_CLR(data->rio_base), pin); |
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sys_clear_bit(RIO_OUT_SET(data->rio_base), pin); |
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} |
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} else if (flags & GPIO_INPUT) { |
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sys_set_bit(RIO_OE_CLR(data->rio_base), pin); |
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sys_set_bits(PADS_CTRL(data->pads_base, pin), |
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PADS_OUTPUT_DISABLE | PADS_INPUT_ENABLE); |
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} |
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/* Set pull up/down */ |
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sys_clear_bits(PADS_CTRL(data->pads_base, pin), |
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PADS_PULL_UP_ENABLE | PADS_PULL_DOWN_ENABLE); |
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if (flags & GPIO_PULL_UP) { |
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sys_set_bits(PADS_CTRL(data->pads_base, pin), PADS_PULL_UP_ENABLE); |
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} else if (flags & GPIO_PULL_DOWN) { |
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sys_set_bits(PADS_CTRL(data->pads_base, pin), PADS_PULL_DOWN_ENABLE); |
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} |
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return 0; |
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} |
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static int gpio_rp1_port_get_raw(const struct device *port, gpio_port_value_t *value) |
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{ |
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struct gpio_rp1_data *data = port->data; |
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*value = sys_read32(RIO_IN(data->rio_base)); |
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return 0; |
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} |
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static int gpio_rp1_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask, |
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gpio_port_value_t value) |
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{ |
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struct gpio_rp1_data *data = port->data; |
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sys_clear_bits(RIO_OUT_SET(data->rio_base), mask); |
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sys_set_bits(RIO_OUT_CLR(data->rio_base), mask); |
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sys_clear_bits(RIO_OUT_CLR(data->rio_base), (value & mask)); |
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sys_set_bits(RIO_OUT_SET(data->rio_base), (value & mask)); |
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return 0; |
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} |
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static int gpio_rp1_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins) |
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{ |
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struct gpio_rp1_data *data = port->data; |
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sys_clear_bits(RIO_OUT_CLR(data->rio_base), pins); |
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sys_set_bits(RIO_OUT_SET(data->rio_base), pins); |
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return 0; |
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} |
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static int gpio_rp1_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins) |
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{ |
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struct gpio_rp1_data *data = port->data; |
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sys_clear_bits(RIO_OUT_SET(data->rio_base), pins); |
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sys_set_bits(RIO_OUT_CLR(data->rio_base), pins); |
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return 0; |
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} |
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static int gpio_rp1_port_toggle_bits(const struct device *port, gpio_port_pins_t pins) |
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{ |
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struct gpio_rp1_data *data = port->data; |
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uint32_t val; |
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val = sys_read32(RIO_OUT(data->rio_base)); |
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/* Low to high */ |
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sys_set_bits(RIO_OUT_SET(data->rio_base), val ^ pins); |
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sys_clear_bits(RIO_OUT_CLR(data->rio_base), val ^ pins); |
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/* High to low */ |
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sys_set_bits(RIO_OUT_CLR(data->rio_base), val & pins); |
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sys_clear_bits(RIO_OUT_SET(data->rio_base), val & pins); |
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return 0; |
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} |
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static DEVICE_API(gpio, gpio_rp1_api) = { |
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.pin_configure = gpio_rp1_pin_configure, |
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.port_get_raw = gpio_rp1_port_get_raw, |
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.port_set_masked_raw = gpio_rp1_port_set_masked_raw, |
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.port_set_bits_raw = gpio_rp1_port_set_bits_raw, |
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.port_clear_bits_raw = gpio_rp1_port_clear_bits_raw, |
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.port_toggle_bits = gpio_rp1_port_toggle_bits, |
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}; |
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static int gpio_rp1_init(const struct device *port) |
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{ |
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const struct gpio_rp1_config *config = port->config; |
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struct gpio_rp1_data *data = port->data; |
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DEVICE_MMIO_NAMED_MAP(port, reg_base, K_MEM_CACHE_NONE); |
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data->gpio_base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->gpio_offset; |
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data->rio_base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->rio_offset; |
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data->pads_base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->pads_offset; |
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return 0; |
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} |
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#define GPIO_RP1_INIT(n) \ |
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static struct gpio_rp1_data gpio_rp1_data_##n; \ |
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\ |
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static const struct gpio_rp1_config gpio_rp1_cfg_##n = { \ |
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.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0)}, \ |
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_INST_PARENT(n)), \ |
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.gpio_offset = DT_INST_REG_ADDR_BY_IDX(n, 0), \ |
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.rio_offset = DT_INST_REG_ADDR_BY_IDX(n, 1), \ |
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.pads_offset = DT_INST_REG_ADDR_BY_IDX(n, 2), \ |
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.ngpios = DT_INST_PROP(n, ngpios), \ |
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}; \ |
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\ |
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DEVICE_DT_INST_DEFINE(n, gpio_rp1_init, NULL, &gpio_rp1_data_##n, &gpio_rp1_cfg_##n, \ |
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POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rp1_api); |
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DT_INST_FOREACH_STATUS_OKAY(GPIO_RP1_INIT)
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