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360 lines
9.7 KiB
360 lines
9.7 KiB
/* |
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* Copyright (c) 2019-2021 Antmicro <www.antmicro.com> |
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* Copyright (c) 2021 Raptor Engineering, LLC <sales@raptorengineering.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT litex_gpio |
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#include <errno.h> |
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#include <zephyr/device.h> |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/types.h> |
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#include <zephyr/sys/util.h> |
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#include <string.h> |
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#include <zephyr/logging/log.h> |
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#include <soc.h> |
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#define SUPPORTED_FLAGS (GPIO_INPUT | GPIO_OUTPUT | \ |
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GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | \ |
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GPIO_ACTIVE_LOW | GPIO_ACTIVE_HIGH) |
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#define GPIO_LOW 0 |
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#define GPIO_HIGH 1 |
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL |
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LOG_MODULE_REGISTER(gpio_litex); |
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static const char *LITEX_LOG_REG_SIZE_NGPIOS_MISMATCH = |
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"Cannot handle all of the gpios with the register of given size\n"; |
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static const char *LITEX_LOG_CANNOT_CHANGE_DIR = |
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"Cannot change port direction selected in device tree\n"; |
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struct gpio_litex_cfg { |
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uint32_t reg_addr; |
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int reg_size; |
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uint32_t ev_pending_addr; |
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uint32_t ev_enable_addr; |
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uint32_t ev_mode_addr; |
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uint32_t ev_edge_addr; |
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int nr_gpios; |
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bool port_is_output; |
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}; |
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struct gpio_litex_data { |
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struct gpio_driver_data common; |
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const struct device *dev; |
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sys_slist_t cb; |
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}; |
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/* Helper macros for GPIO */ |
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#define DEV_GPIO_CFG(dev) \ |
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((const struct gpio_litex_cfg *)(dev)->config) |
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/* Helper functions for bit / port access */ |
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static inline void set_bit(const struct gpio_litex_cfg *config, |
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uint32_t bit, bool val) |
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{ |
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int regv, new_regv; |
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regv = litex_read(config->reg_addr, config->reg_size); |
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new_regv = (regv & ~BIT(bit)) | (val << bit); |
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litex_write(config->reg_addr, config->reg_size, new_regv); |
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} |
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static inline uint32_t get_bit(const struct gpio_litex_cfg *config, uint32_t bit) |
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{ |
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int regv = litex_read(config->reg_addr, config->reg_size); |
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return !!(regv & BIT(bit)); |
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} |
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static inline void set_port(const struct gpio_litex_cfg *config, uint32_t value) |
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{ |
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litex_write(config->reg_addr, config->reg_size, value); |
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} |
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static inline uint32_t get_port(const struct gpio_litex_cfg *config) |
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{ |
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int regv = litex_read(config->reg_addr, config->reg_size); |
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return (regv & BIT_MASK(config->nr_gpios)); |
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} |
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/* Driver functions */ |
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static int gpio_litex_configure(const struct device *dev, |
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gpio_pin_t pin, gpio_flags_t flags) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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if (flags & ~SUPPORTED_FLAGS) { |
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return -ENOTSUP; |
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} |
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if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) { |
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/* Pin cannot be configured as input and output */ |
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return -ENOTSUP; |
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} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) { |
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/* Pin has to be configured as input or output */ |
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return -ENOTSUP; |
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} |
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if (flags & GPIO_OUTPUT) { |
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if (!gpio_config->port_is_output) { |
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LOG_ERR("%s", LITEX_LOG_CANNOT_CHANGE_DIR); |
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return -EINVAL; |
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} |
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if (flags & GPIO_OUTPUT_INIT_HIGH) { |
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set_bit(gpio_config, pin, GPIO_HIGH); |
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} else if (flags & GPIO_OUTPUT_INIT_LOW) { |
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set_bit(gpio_config, pin, GPIO_LOW); |
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} |
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} else { |
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if (gpio_config->port_is_output) { |
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LOG_ERR("%s", LITEX_LOG_CANNOT_CHANGE_DIR); |
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return -EINVAL; |
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} |
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} |
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return 0; |
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} |
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static int gpio_litex_port_get_raw(const struct device *dev, |
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gpio_port_value_t *value) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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*value = get_port(gpio_config); |
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return 0; |
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} |
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static int gpio_litex_port_set_masked_raw(const struct device *dev, |
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gpio_port_pins_t mask, |
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gpio_port_value_t value) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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uint32_t port_val; |
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port_val = get_port(gpio_config); |
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port_val = (port_val & ~mask) | (value & mask); |
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set_port(gpio_config, port_val); |
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return 0; |
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} |
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static int gpio_litex_port_set_bits_raw(const struct device *dev, |
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gpio_port_pins_t pins) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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uint32_t port_val; |
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port_val = get_port(gpio_config); |
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port_val |= pins; |
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set_port(gpio_config, port_val); |
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return 0; |
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} |
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static int gpio_litex_port_clear_bits_raw(const struct device *dev, |
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gpio_port_pins_t pins) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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uint32_t port_val; |
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port_val = get_port(gpio_config); |
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port_val &= ~pins; |
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set_port(gpio_config, port_val); |
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return 0; |
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} |
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static int gpio_litex_port_toggle_bits(const struct device *dev, |
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gpio_port_pins_t pins) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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uint32_t port_val; |
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port_val = get_port(gpio_config); |
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port_val ^= pins; |
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set_port(gpio_config, port_val); |
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return 0; |
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} |
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static void gpio_litex_irq_handler(const struct device *dev) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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struct gpio_litex_data *data = dev->data; |
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uint8_t int_status = |
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litex_read(gpio_config->ev_pending_addr, gpio_config->reg_size); |
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uint8_t ev_enabled = |
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litex_read(gpio_config->ev_enable_addr, gpio_config->reg_size); |
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/* clear events */ |
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litex_write(gpio_config->ev_pending_addr, gpio_config->reg_size, |
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int_status); |
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gpio_fire_callbacks(&data->cb, dev, int_status & ev_enabled); |
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} |
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static int gpio_litex_manage_callback(const struct device *dev, |
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struct gpio_callback *callback, bool set) |
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{ |
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struct gpio_litex_data *data = dev->data; |
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return gpio_manage_callback(&data->cb, callback, set); |
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} |
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static int gpio_litex_pin_interrupt_configure(const struct device *dev, |
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gpio_pin_t pin, |
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enum gpio_int_mode mode, |
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enum gpio_int_trig trig) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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if (gpio_config->port_is_output == true) { |
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return -ENOTSUP; |
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} |
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if (mode == GPIO_INT_MODE_EDGE) { |
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uint8_t ev_enabled = litex_read(gpio_config->ev_enable_addr, |
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gpio_config->reg_size); |
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uint8_t ev_mode = litex_read(gpio_config->ev_mode_addr, |
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gpio_config->reg_size); |
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uint8_t ev_edge = litex_read(gpio_config->ev_edge_addr, |
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gpio_config->reg_size); |
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litex_write(gpio_config->ev_enable_addr, gpio_config->reg_size, |
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ev_enabled | BIT(pin)); |
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if (trig == GPIO_INT_TRIG_HIGH) { |
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/* Change mode to 'edge' and edge to 'rising' */ |
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litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size, |
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ev_mode & ~BIT(pin)); |
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litex_write(gpio_config->ev_edge_addr, gpio_config->reg_size, |
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ev_edge & ~BIT(pin)); |
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} else if (trig == GPIO_INT_TRIG_LOW) { |
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/* Change mode to 'edge' and edge to 'falling' */ |
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litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size, |
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ev_mode & ~BIT(pin)); |
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litex_write(gpio_config->ev_edge_addr, gpio_config->reg_size, |
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ev_edge | BIT(pin)); |
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} else if (trig == GPIO_INT_TRIG_BOTH) { |
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/* Change mode to 'change' */ |
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litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size, |
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ev_mode | BIT(pin)); |
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} |
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return 0; |
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} |
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if (mode == GPIO_INT_DISABLE) { |
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uint8_t ev_enabled = litex_read(gpio_config->ev_enable_addr, |
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gpio_config->reg_size); |
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litex_write(gpio_config->ev_enable_addr, gpio_config->reg_size, |
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ev_enabled & ~BIT(pin)); |
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return 0; |
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} |
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return -ENOTSUP; |
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} |
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#ifdef CONFIG_GPIO_GET_DIRECTION |
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static int gpio_litex_port_get_direction(const struct device *dev, gpio_port_pins_t map, |
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gpio_port_pins_t *inputs, gpio_port_pins_t *outputs) |
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{ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); |
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map &= gpio_config->port_pin_mask; |
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if (inputs != NULL) { |
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*inputs = map & (!gpio_config->port_is_output); |
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} |
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if (outputs != NULL) { |
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*outputs = map & (gpio_config->port_is_output); |
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} |
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return 0; |
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} |
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#endif /* CONFIG_GPIO_GET_DIRECTION */ |
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static DEVICE_API(gpio, gpio_litex_driver_api) = { |
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.pin_configure = gpio_litex_configure, |
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.port_get_raw = gpio_litex_port_get_raw, |
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.port_set_masked_raw = gpio_litex_port_set_masked_raw, |
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.port_set_bits_raw = gpio_litex_port_set_bits_raw, |
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.port_clear_bits_raw = gpio_litex_port_clear_bits_raw, |
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.port_toggle_bits = gpio_litex_port_toggle_bits, |
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.pin_interrupt_configure = gpio_litex_pin_interrupt_configure, |
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.manage_callback = gpio_litex_manage_callback, |
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#ifdef CONFIG_GPIO_GET_DIRECTION |
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.port_get_direction = gpio_litex_port_get_direction, |
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#endif /* CONFIG_GPIO_GET_DIRECTION */ |
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}; |
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/* Device Instantiation */ |
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#define GPIO_LITEX_IRQ_INIT(n) \ |
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do { \ |
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \ |
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gpio_litex_irq_handler, \ |
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DEVICE_DT_INST_GET(n), 0); \ |
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\ |
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irq_enable(DT_INST_IRQN(n)); \ |
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} while (false) |
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#define GPIO_LITEX_INIT(n) \ |
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static int gpio_litex_port_init_##n(const struct device *dev); \ |
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\ |
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static const struct gpio_litex_cfg gpio_litex_cfg_##n = { \ |
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.reg_addr = DT_INST_REG_ADDR(n), \ |
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.reg_size = DT_INST_REG_SIZE(n), \ |
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.nr_gpios = DT_INST_PROP(n, ngpios), \ |
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), ( \ |
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.ev_mode_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_mode), \ |
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.ev_edge_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_edge), \ |
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.ev_pending_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_pend), \ |
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.ev_enable_addr = DT_INST_REG_ADDR_BY_NAME(n, irq_en), \ |
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)) \ |
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.port_is_output = DT_INST_PROP(n, port_is_output), \ |
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}; \ |
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static struct gpio_litex_data gpio_litex_data_##n; \ |
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\ |
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DEVICE_DT_INST_DEFINE(n, \ |
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gpio_litex_port_init_##n, \ |
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NULL, \ |
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&gpio_litex_data_##n, \ |
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&gpio_litex_cfg_##n, \ |
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POST_KERNEL, \ |
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CONFIG_GPIO_INIT_PRIORITY, \ |
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&gpio_litex_driver_api \ |
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); \ |
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\ |
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static int gpio_litex_port_init_##n(const struct device *dev) \ |
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{ \ |
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const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); \ |
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\ |
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/* Check if gpios fit in declared register space */ \ |
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/* Number of subregisters times size in bits */ \ |
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const int max_gpios_can_fit = DT_INST_REG_SIZE(n) / 4 \ |
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* CONFIG_LITEX_CSR_DATA_WIDTH; \ |
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if (gpio_config->nr_gpios > max_gpios_can_fit) { \ |
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LOG_ERR("%s", LITEX_LOG_REG_SIZE_NGPIOS_MISMATCH); \ |
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return -EINVAL; \ |
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} \ |
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\ |
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ |
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(GPIO_LITEX_IRQ_INIT(n);)) \ |
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return 0; \ |
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} |
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DT_INST_FOREACH_STATUS_OKAY(GPIO_LITEX_INIT)
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