zephyr/dts/bindings/fpga/lattice,ice40-fpga.yaml

# Copyright (c) 2022 Meta
# SPDX-License-Identifier: Apache-2.0

description: Lattice iCE40 FPGA

compatible: "lattice,ice40-fpga"

include: spi-device.yaml

properties:
  load-mode-bitbang:
    type: boolean
    description: |
      Select the bitbang mode for loading the bitstream into the FPGA.
      This is a workaround to meet the timing requirements fo the iCE40
      on low-end microcontrollers.
      This option requires clk-gpios, pico-gpios, gpios-set-reg, and
      gpios-clear-reg to be defined.      
  cdone-gpios:
    type: phandle-array
    required: true
    description: |
      Configuration Done output from iCE40.
      Example usage:
      cdone-gpios = <&gpio0 0 0>;      
  creset-gpios:
    type: phandle-array
    required: true
    description: |
      Configuration Reset input on iCE40.
      Example usage:
      creset-gpios = <&gpio0 1 GPIO_PUSH_PULL);      
  clk-gpios:
    type: phandle-array
    description: |
      SPI Clock GPIO input on iCE40.
      Example usage:
      clk-gpios = <&gpio0 5 GPIO_PUSH_PULL>;      
  pico-gpios:
    type: phandle-array
    description: |
      Peripheral-In Controller-Out GPIO input on iCE40.
      Example usage:
      pico-gpios = <&gpio0 7 GPIO_PUSH_PULL>;      
  gpios-set-reg:
    type: int
    description: |
      Register address for setting a GPIO.
      Example usage:
      gpios-set-reg = <0x60004008>;      
  gpios-clear-reg:
    type: int
    description: |
      Register address for clearing a GPIO.
      Example usage:
      gpios-clear-reg = <0x6000400c>;      
  mhz-delay-count:
    type: int
    description: |
      in order to create a 1 MHz square wave in the following
      process.
      while(true) {
        *gpios_set_reg |= BIT(n);
        for(int i = mhz_delay_count; i > 0; --i);
        *gpios_clear_reg |= BIT(n);
        for(int i = mhz_delay_count; i > 0; --i);
      }
      Example usage / default:
      mhz-delay-count = <0>;      
  creset-delay-us:
    type: int
    default: 1
    description: |
      Delay (in microseconds) between asserting CRESET_B and releasing CRESET_B.
      The datasheet specifies a minimum of 200ns, therefore the default is set
      to 1us.      
  config-delay-us:
    type: int
    default: 1200
    description: |
      Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory.
      The datasheet specifies a minimum of 1200us, which is the default.      
  leading-clocks:
    type: int
    default: 8
    description: |
      Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high.
      The datasheet specifies 8 dummy cycles, which is the default.      
  trailing-clocks:
    type: int
    default: 49
    description: |
      After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high.
      The datasheet specifies 49 dummy cycles, which is the default.