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72 lines
1.2 KiB
72 lines
1.2 KiB
/* |
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* Copyright 2021,2023 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/dts-v1/; |
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#include <nxp/nxp_rt11xx_cm4.dtsi> |
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#include "mimxrt1170_evk.dtsi" |
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/ { |
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model = "NXP MIMXRT1170-EVK board"; |
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compatible = "nxp,mimxrt1176"; |
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chosen { |
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/* |
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* Note: when using DMA, the SRAM region must be set to |
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* a memory region that is not cached by the chip. If the chosen |
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* sram region is changed and DMA is in use, you will |
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* encounter issues! |
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*/ |
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zephyr,sram = &sram1; |
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zephyr,console = &lpuart1; |
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zephyr,shell-uart = &lpuart1; |
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zephyr,canbus = &flexcan2; |
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zephyr,flash-controller = &is25wp128; |
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zephyr,flash = &ocram; |
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nxp,m4-partition = &slot1_partition; |
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zephyr,ipc = &mailbox_b; |
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}; |
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sdram0: memory@80000000 { |
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/* Winbond W9825G6KH-5I */ |
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device_type = "memory"; |
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reg = <0x80000000 DT_SIZE_M(64)>; |
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}; |
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}; |
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&lpuart1 { |
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status = "okay"; |
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current-speed = <115200>; |
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}; |
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&lpi2c1 { |
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status = "okay"; |
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}; |
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/* GPT and Systick are enabled. If power management is enabled, the GPT |
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* timer will be used instead of systick, as allows the core clock to |
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* be gated. |
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*/ |
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&gpt_hw_timer { |
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status = "okay"; |
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}; |
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&systick { |
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status = "okay"; |
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}; |
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&sai1 { |
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status = "okay"; |
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}; |
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&edma_lpsr0 { |
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status = "okay"; |
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}; |
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&mailbox_b { |
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status = "okay"; |
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};
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