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67 lines
1.4 KiB
67 lines
1.4 KiB
/* |
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* Copyright (c) 2020 Linaro Limited |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** |
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* @file |
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* @brief System/hardware module for STM32L5 processor |
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*/ |
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#include <zephyr/device.h> |
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#include <zephyr/init.h> |
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#include <stm32_ll_bus.h> |
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#include <stm32_ll_pwr.h> |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h> |
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#include <zephyr/irq.h> |
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#include <stm32l5xx_ll_icache.h> |
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#include <zephyr/logging/log.h> |
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL |
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LOG_MODULE_REGISTER(soc); |
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/** |
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* @brief Perform basic hardware initialization at boot. |
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* |
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* This needs to be run from the very beginning. |
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* So the init priority has to be 0 (zero). |
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* |
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* @return 0 |
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*/ |
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static int stm32l5_init(const struct device *arg) |
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{ |
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uint32_t key; |
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ARG_UNUSED(arg); |
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/* Enable ICACHE */ |
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while (LL_ICACHE_IsActiveFlag_BUSY()) { |
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} |
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LL_ICACHE_Enable(); |
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key = irq_lock(); |
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/* Install default handler that simply resets the CPU |
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* if configured in the kernel, NOP otherwise |
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*/ |
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NMI_INIT(); |
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irq_unlock(key); |
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/* Update CMSIS SystemCoreClock variable (HCLK) */ |
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/* At reset, system core clock is set to 4 MHz from MSI */ |
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SystemCoreClock = 4000000; |
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/* Enable Scale 0 to achieve 110MHz */ |
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); |
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0); |
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/* Disable USB Type-C dead battery pull-down behavior */ |
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LL_PWR_DisableUCPDDeadBattery(); |
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return 0; |
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} |
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SYS_INIT(stm32l5_init, PRE_KERNEL_1, 0);
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