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69 lines
1.7 KiB
69 lines
1.7 KiB
/* |
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* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com> |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** |
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* @file |
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* @brief System/hardware module for STM32L0 processor |
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*/ |
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#include <zephyr/device.h> |
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#include <zephyr/init.h> |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/linker/linker-defs.h> |
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#include <string.h> |
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#include <stm32_ll_bus.h> |
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#include <stm32_ll_pwr.h> |
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#include <stm32_ll_bus.h> |
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/** |
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* @brief Perform basic hardware initialization at boot. |
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* |
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* This needs to be run from the very beginning. |
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* So the init priority has to be 0 (zero). |
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* |
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* @return 0 |
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*/ |
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static int stm32l0_init(const struct device *arg) |
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{ |
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uint32_t key; |
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ARG_UNUSED(arg); |
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key = irq_lock(); |
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/* Install default handler that simply resets the CPU |
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* if configured in the kernel, NOP otherwise |
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*/ |
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NMI_INIT(); |
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irq_unlock(key); |
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/* Update CMSIS SystemCoreClock variable (HCLK) */ |
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/* At reset, system core clock is set to 2.1 MHz from MSI */ |
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SystemCoreClock = 2097152; |
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/* Default Voltage scaling range selection (range2) |
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* doesn't allow to configure Max frequency |
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* switch to range1 to match any frequency |
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*/ |
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); |
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); |
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/* On STM32L0, there are some hardfault when enabling DBGMCU bit: |
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* Sleep, Stop or Standby. |
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* See https://github.com/zephyrproject-rtos/zephyr/issues/#37119 |
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* For unclear reason, enabling DMA clock fixes this issue |
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* (similarly than it fixes |
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* https://github.com/zephyrproject-rtos/zephyr/issues/#34324 ) |
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*/ |
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); |
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return 0; |
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} |
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SYS_INIT(stm32l0_init, PRE_KERNEL_1, 0);
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