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55 lines
1.1 KiB
55 lines
1.1 KiB
/* |
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* Copyright (c) 2016 Open-RnD Sp. z o.o. |
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* Copyright (c) 2016 Linaro Limited. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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/** |
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* @file |
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* @brief System/hardware module for STM32F4 processor |
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*/ |
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#include <zephyr/device.h> |
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#include <zephyr/init.h> |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h> |
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#include <zephyr/irq.h> |
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#include <stm32_ll_system.h> |
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/** |
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* @brief Perform basic hardware initialization at boot. |
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* |
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* This needs to be run from the very beginning. |
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* So the init priority has to be 0 (zero). |
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* |
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* @return 0 |
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*/ |
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static int st_stm32f4_init(const struct device *arg) |
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{ |
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uint32_t key; |
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ARG_UNUSED(arg); |
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/* Enable ART Flash cache accelerator for both instruction and data */ |
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LL_FLASH_EnableInstCache(); |
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LL_FLASH_EnableDataCache(); |
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key = irq_lock(); |
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/* Install default handler that simply resets the CPU |
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* if configured in the kernel, NOP otherwise |
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*/ |
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NMI_INIT(); |
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irq_unlock(key); |
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/* Update CMSIS SystemCoreClock variable (HCLK) */ |
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/* At reset, system core clock is set to 16 MHz from HSI */ |
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SystemCoreClock = 16000000; |
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return 0; |
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} |
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SYS_INIT(st_stm32f4_init, PRE_KERNEL_1, 0);
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