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55 lines
1.3 KiB
55 lines
1.3 KiB
/* |
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* Copyright (c) 2020-2022 IoT.bzh |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h> |
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#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h> |
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#include <zephyr/irq.h> |
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#include "clock_control_renesas_cpg_mssr.h" |
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static void rcar_cpg_reset(uint32_t base_address, uint32_t reg, uint32_t bit) |
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{ |
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rcar_cpg_write(base_address, srcr[reg], BIT(bit)); |
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rcar_cpg_write(base_address, SRSTCLR(reg), BIT(bit)); |
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} |
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void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val) |
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{ |
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sys_write32(~val, base_address + CPGWPR); |
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sys_write32(val, base_address + reg); |
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/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ |
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k_sleep(K_USEC(35)); |
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} |
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int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable) |
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{ |
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uint32_t reg = module / 100; |
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uint32_t bit = module % 100; |
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uint32_t bitmask = BIT(bit); |
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uint32_t reg_val; |
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unsigned int key; |
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__ASSERT((bit < 32) && reg < ARRAY_SIZE(mstpcr), "Invalid module number for cpg clock: %d", |
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module); |
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key = irq_lock(); |
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reg_val = sys_read32(base_address + mstpcr[reg]); |
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if (enable) { |
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reg_val &= ~bitmask; |
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} else { |
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reg_val |= bitmask; |
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} |
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sys_write32(reg_val, base_address + mstpcr[reg]); |
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if (!enable) { |
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rcar_cpg_reset(base_address, reg, bit); |
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} |
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irq_unlock(key); |
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return 0; |
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}
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