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145 lines
4.7 KiB
145 lines
4.7 KiB
/* |
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* Copyright 2022 Meta Platforms, Inc. and its affiliates. |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_DRIVERS_SERIAL_UART_CDNS_H_ |
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#define ZEPHYR_DRIVERS_SERIAL_UART_CDNS_H_ |
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#include <zephyr/arch/cpu.h> |
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#include <zephyr/drivers/uart.h> |
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#include <zephyr/kernel.h> |
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enum csr_parity_val { |
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EVEN_PARITY_VAL, |
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ODD_PARITY_VAL, |
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SPACE_PARITY_VAL, |
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MARK_PARITY_VAL, |
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NO_PARITY_VAL |
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}; |
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/* @brief Control(CTRL) Registers offset 0x00 */ |
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#define CTRL_STPBRK_MASK (1 << 8) |
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#define CTRL_STPBRK_SHIFT (8) |
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#define CTRL_STTBRK_MASK (1 << 7) |
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#define CTRL_STTBRK_SHIFT (7) |
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#define CTRL_RSTTO_MASK (1 << 6) |
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#define CTRL_RSTTO_SHIFT (6) |
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#define CTRL_TXDIS_MASK (1 << 5) |
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#define CTRL_TXDIS_SHIFT (5) |
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#define CTRL_TXEN_MASK (1 << 4) |
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#define CTRL_TXEN_SHIFT (4) |
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#define CTRL_RXDIS_MASK (1 << 3) |
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#define CTRL_RXDIS_SHIFT (3) |
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#define CTRL_RXEN_MASK (1 << 2) |
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#define CTRL_RXEN_SHIFT (2) |
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#define CTRL_TXRES_MASK (1 << 1) |
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#define CTRL_TXRES_SHIFT (1) |
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#define CTRL_RXRES_MASK (1 << 0) |
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#define CTRL_RXRES_SHIFT (0) |
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/* @brief Mode Registers offset 0x04 */ |
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#define MODE_WSIZE_MASK (0x3 << 12) |
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#define MODE_WSIZE_SHIFT (12) |
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#define MODE_WSIZE_SIZE (2) |
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#define MODE_IRMODE_MASK (1 << 11) |
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#define MODE_IRMODE_SHIFT (11) |
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#define MODE_UCLKEN_MASK (1 << 10) |
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#define MODE_UCLKEN_SHIFT (10) |
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#define MODE_CHMOD_MASK (0x3 << 8) |
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#define MODE_CHMOD_SHIFT (8) |
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#define MODE_CHMOD_SIZE (2) |
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#define MODE_NBSTOP_MASK (0x3 << 6) |
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#define MODE_NBSTOP_SHIFT (6) |
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#define MODE_NBSTOP_SIZE (2) |
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#define MODE_PAR_MASK (0x7 << 3) |
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#define MODE_PAR_SHIFT (3) |
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#define MODE_PAR_SIZE (3) |
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#define MODE_CHRL_MASK (0x3 << 1) |
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#define MODE_CHRL_SHIFT (2) |
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#define MODE_CHRL_SIZE (2) |
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#define MODE_CLKS_MASK (1 << 0) |
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#define MODE_CLKS_SHIFT (0) |
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/* @brief IER, IDR, IMR and CSIR Registers offset 0x08, 0xC, 0x10 and 0x14 */ |
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#define CSR_RBRK_MASK (1 << 13) |
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#define CSR_RBRK_SHIFT (13) |
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#define CSR_TOVR_MASK (1 << 12) |
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#define CSR_TOVR_SHIFT (12) |
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#define CSR_TNFUL_MASK (1 << 11) |
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#define CSR_TNFUL_SHIFT (11) |
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#define CSR_TTRIG_MASK (1 << 10) |
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#define CSR_TTRIG_SHIFT (10) |
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#define CSR_DMSI_MASK (1 << 9) |
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#define CSR_DMSI_SHIFT (9) |
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#define CSR_TOUT_MASK (1 << 8) |
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#define CSR_TOUT_SHIFT (8) |
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#define CSR_PARE_MASK (1 << 7) |
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#define CSR_PARE_SHIFT (7) |
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#define CSR_FRAME_MASK (1 << 6) |
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#define CSR_FRAME_SHIFT (6) |
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#define CSR_ROVR_MASK (1 << 5) |
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#define CSR_ROVR_SHIFT (5) |
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#define CSR_TFUL_MASK (1 << 4) |
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#define CSR_TFUL_SHIFT (4) |
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#define CSR_TEMPTY_MASK (1 << 3) |
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#define CSR_TEMPTY_SHIFT (3) |
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#define CSR_RFUL_MASK (1 << 2) |
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#define CSR_RFUL_SHIFT (2) |
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#define CSR_REMPTY_MASK (1 << 1) |
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#define CSR_REMPTY_SHIFT (1) |
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#define CSR_RTRIG_MASK (1 << 0) |
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#define CSR_RTRIG_SHIFT (0) |
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#define RXDATA_MASK 0xFF /* Receive Data Mask */ |
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#define MAX_FIFO_SIZE (64) |
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#define DEFAULT_RTO_PERIODS_FACTOR 8 |
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#define SET_VAL32(name, val) (((uint32_t)(val) << name##_SHIFT) & name##_MASK) |
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#define CDNS_PARTITY_MAP(parity) \ |
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(parity == UART_CFG_PARITY_NONE) ? NO_PARITY_VAL \ |
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: (parity == UART_CFG_PARITY_ODD) ? ODD_PARITY_VAL \ |
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: (parity == UART_CFG_PARITY_MARK) ? MARK_PARITY_VAL \ |
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: (parity == UART_CFG_PARITY_SPACE) ? SPACE_PARITY_VAL \ |
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: EVEN_PARITY_VAL |
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struct uart_cdns_regs { |
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volatile uint32_t ctrl; /* Control Register */ |
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volatile uint32_t mode; /* Mode Register */ |
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volatile uint32_t intr_enable; /* Interrupt Enable Register */ |
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volatile uint32_t intr_disable; /* Interrupt Disable Register */ |
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volatile uint32_t intr_mask; /* Interrupt Mask Register */ |
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volatile uint32_t channel_intr_status; /* Channel Interrupt Status Register */ |
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volatile uint32_t baud_rate_gen; /* Baud Rate Generator Register */ |
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volatile uint32_t rx_timeout; /* Receiver Timeout Register */ |
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volatile uint32_t rx_fifo_trigger_level; /* Receiver FIFO Trigger Level Register */ |
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volatile uint32_t modem_control; /* Modem Control Register */ |
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volatile uint32_t modem_status; /* Modem Status Register */ |
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volatile uint32_t channel_status; /* Channel status */ |
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volatile uint32_t rx_tx_fifo; /* RX TX FIFO Register */ |
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volatile uint32_t baud_rate_div; /* Baud Rate Divider Register */ |
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volatile uint32_t flow_ctrl_delay; /* Flow Control Delay Register */ |
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volatile uint32_t rpwr; /* IR Minimum Received Pulse Register */ |
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volatile uint32_t tpwr; /* IR TRansmitted Pulse Width Register */ |
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volatile uint32_t tx_fifo_trigger_level; /* Transmitter FIFO trigger level */ |
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volatile uint32_t rbrs; /* RX FIFO Byte Status Register */ |
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}; |
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struct uart_cdns_device_config { |
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uint32_t port; |
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uint32_t bdiv; |
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uint32_t sys_clk_freq; |
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uint32_t baud_rate; |
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uint8_t parity; |
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void (*cfg_func)(void); |
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}; |
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struct uart_cdns_data { |
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN |
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uart_irq_callback_user_data_t callback; |
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void *cb_data; |
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#endif |
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}; |
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#endif /* ZEPHYR_DRIVERS_SERIAL_UART_CDNS_H_ */
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