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201 lines
6.5 KiB
201 lines
6.5 KiB
/* |
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* Copyright (c) 2024 Silicon Laboratories Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT silabs_siwx91x_gpio_uulp |
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#include "sl_si91x_driver_gpio.h" |
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#include "sl_status.h" |
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#include <errno.h> |
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#include <zephyr/sys/util.h> |
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#include <zephyr/irq.h> |
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/* Zephyr GPIO header must be included after driver, due to symbol conflicts |
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* for GPIO_INPUT and GPIO_OUTPUT between preprocessor macros in the Zephyr |
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* API and struct member register definitions for the SiWx91x device. |
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*/ |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#define UULP_GPIO_COUNT 5 |
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#define UULP_REG_INTERRUPT_CONFIG 0x10 |
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/* Types */ |
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struct gpio_siwx91x_uulp_config { |
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/* gpio_driver_config needs to be first */ |
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struct gpio_driver_config common; |
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}; |
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struct gpio_siwx91x_uulp_data { |
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/* gpio_driver_data needs to be first */ |
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struct gpio_driver_data common; |
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/* port ISR callback routine address */ |
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sys_slist_t callbacks; |
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}; |
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/* Functions */ |
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static int gpio_siwx91x_uulp_pin_configure(const struct device *dev, gpio_pin_t pin, |
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gpio_flags_t flags) |
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{ |
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if (flags & (GPIO_SINGLE_ENDED | GPIO_PULL_UP | GPIO_PULL_DOWN)) { |
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return -ENOTSUP; |
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} |
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/* Enable input */ |
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sl_si91x_gpio_select_uulp_npss_receiver(pin, (flags & GPIO_INPUT) ? 1 : 0); |
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/* Select GPIO mode */ |
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sl_si91x_gpio_set_uulp_npss_pin_mux(pin, 0); |
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if (flags & GPIO_OUTPUT_INIT_HIGH) { |
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sl_si91x_gpio_set_uulp_npss_pin_value(pin, 1); |
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} else if (flags & GPIO_OUTPUT_INIT_LOW) { |
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sl_si91x_gpio_set_uulp_npss_pin_value(pin, 0); |
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} |
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/* Enable output */ |
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sl_si91x_gpio_set_uulp_npss_direction(pin, (flags & GPIO_OUTPUT) ? 0 : 1); |
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return 0; |
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} |
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static int gpio_siwx91x_uulp_port_get(const struct device *port, gpio_port_value_t *value) |
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{ |
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for (size_t i = 0; i < UULP_GPIO_COUNT; i++) { |
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WRITE_BIT(*value, i, sl_si91x_gpio_get_uulp_npss_pin(i)); |
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} |
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return 0; |
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} |
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static int gpio_siwx91x_uulp_port_set_masked(const struct device *port, gpio_port_pins_t mask, |
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gpio_port_value_t value) |
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{ |
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for (size_t i = 0; i < UULP_GPIO_COUNT; i++) { |
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if (mask & BIT(i)) { |
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sl_si91x_gpio_set_uulp_npss_pin_value(i, FIELD_GET(BIT(i), value)); |
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} |
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} |
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return 0; |
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} |
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static int gpio_siwx91x_uulp_port_set_bits(const struct device *port, gpio_port_pins_t pins) |
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{ |
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for (size_t i = 0; i < UULP_GPIO_COUNT; i++) { |
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if (FIELD_GET(BIT(i), pins)) { |
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sl_si91x_gpio_set_uulp_npss_pin_value(i, 1); |
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} |
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} |
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return 0; |
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} |
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static int gpio_siwx91x_uulp_port_clear_bits(const struct device *port, gpio_port_pins_t pins) |
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{ |
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for (size_t i = 0; i < UULP_GPIO_COUNT; i++) { |
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if (FIELD_GET(BIT(i), pins)) { |
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sl_si91x_gpio_set_uulp_npss_pin_value(i, 0); |
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} |
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} |
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return 0; |
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} |
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static int gpio_siwx91x_uulp_port_toggle_bits(const struct device *port, gpio_port_pins_t pins) |
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{ |
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for (size_t i = 0; i < UULP_GPIO_COUNT; i++) { |
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if (FIELD_GET(BIT(i), pins)) { |
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sl_si91x_gpio_toggle_uulp_npss_pin(i); |
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} |
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} |
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return 0; |
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} |
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static int gpio_siwx91x_uulp_manage_callback(const struct device *port, |
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struct gpio_callback *callback, bool set) |
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{ |
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struct gpio_siwx91x_uulp_data *data = port->data; |
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return gpio_manage_callback(&data->callbacks, callback, set); |
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} |
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static int gpio_siwx91x_uulp_interrupt_configure(const struct device *port, gpio_pin_t pin, |
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enum gpio_int_mode mode, enum gpio_int_trig trig) |
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{ |
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uint32_t flags = 0; |
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if (mode == GPIO_INT_MODE_DISABLED) { |
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sl_si91x_gpio_configure_uulp_interrupt(flags, pin); |
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sl_si91x_gpio_clear_uulp_interrupt(BIT(pin)); |
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sl_si91x_gpio_mask_uulp_npss_interrupt(BIT(pin)); |
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} else { |
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if (trig == GPIO_INT_TRIG_LOW) { |
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flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_FALL_EDGE |
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: SL_GPIO_INTERRUPT_LEVEL_LOW; |
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} else if (trig == GPIO_INT_TRIG_HIGH) { |
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flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_RISE_EDGE |
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: SL_GPIO_INTERRUPT_LEVEL_HIGH; |
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} else if (trig == GPIO_INT_TRIG_BOTH) { |
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/* SL_GPIO_INTERRUPT_RISE_FALL_EDGE would make more sense, but HAL |
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* implementation is buggy. |
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*/ |
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flags = SL_GPIO_INTERRUPT_RISE_EDGE | SL_GPIO_INTERRUPT_FALL_EDGE; |
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} |
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sl_si91x_gpio_configure_uulp_interrupt(flags, pin); |
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} |
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return 0; |
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} |
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static void gpio_siwx91x_uulp_isr(const struct device *port) |
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{ |
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struct gpio_siwx91x_uulp_data *data = port->data; |
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uint8_t pins = sl_si91x_gpio_get_uulp_interrupt_status(); |
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sl_si91x_gpio_clear_uulp_interrupt(pins); |
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gpio_fire_callbacks(&data->callbacks, port, pins); |
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} |
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static DEVICE_API(gpio, gpio_siwx91x_uulp_api) = { |
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.pin_configure = gpio_siwx91x_uulp_pin_configure, |
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#ifdef CONFIG_GPIO_GET_CONFIG |
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.pin_get_config = NULL, |
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#endif |
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.port_get_raw = gpio_siwx91x_uulp_port_get, |
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.port_set_masked_raw = gpio_siwx91x_uulp_port_set_masked, |
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.port_set_bits_raw = gpio_siwx91x_uulp_port_set_bits, |
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.port_clear_bits_raw = gpio_siwx91x_uulp_port_clear_bits, |
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.port_toggle_bits = gpio_siwx91x_uulp_port_toggle_bits, |
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.pin_interrupt_configure = gpio_siwx91x_uulp_interrupt_configure, |
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.manage_callback = gpio_siwx91x_uulp_manage_callback, |
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.get_pending_int = NULL, |
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#ifdef CONFIG_GPIO_GET_DIRECTION |
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.port_get_direction = NULL, |
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#endif |
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}; |
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#define GPIO_PORT_INIT(idx) \ |
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static const struct gpio_siwx91x_uulp_config gpio_siwx91x_port_config##idx = { \ |
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.common.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \ |
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}; \ |
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static struct gpio_siwx91x_uulp_data gpio_siwx91x_port_data##idx; \ |
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\ |
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static int gpio_siwx91x_init_uulp_##idx(const struct device *dev) \ |
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{ \ |
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sys_write32(0, DT_INST_REG_ADDR_BY_NAME(idx, int) + UULP_REG_INTERRUPT_CONFIG); \ |
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IRQ_CONNECT(DT_INST_IRQ(idx, irq), DT_INST_IRQ(idx, priority), \ |
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gpio_siwx91x_uulp_isr, DEVICE_DT_GET(DT_DRV_INST(idx)), 0); \ |
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irq_enable(DT_INST_IRQ(idx, irq)); \ |
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return 0; \ |
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} \ |
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DEVICE_DT_INST_DEFINE(idx, gpio_siwx91x_init_uulp_##idx, NULL, \ |
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&gpio_siwx91x_port_data##idx, &gpio_siwx91x_port_config##idx, \ |
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PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_siwx91x_uulp_api); |
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DT_INST_FOREACH_STATUS_OKAY(GPIO_PORT_INIT)
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