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44 lines
934 B
44 lines
934 B
/* |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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* Copyright (C) 2021-2022, Intel Corporation |
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* |
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*/ |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/clock_control/clock_agilex_ll.h> |
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#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h> |
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static int clk_get_rate(const struct device *dev, |
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clock_control_subsys_t sub_system, |
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uint32_t *rate) |
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{ |
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ARG_UNUSED(dev); |
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switch ((intptr_t) sub_system) { |
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case INTEL_SOCFPGA_CLOCK_MPU: |
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*rate = get_mpu_clk(); |
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break; |
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case INTEL_SOCFPGA_CLOCK_WDT: |
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*rate = get_wdt_clk(); |
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break; |
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case INTEL_SOCFPGA_CLOCK_UART: |
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*rate = get_uart_clk(); |
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break; |
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case INTEL_SOCFPGA_CLOCK_MMC: |
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*rate = get_mmc_clk(); |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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return 0; |
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} |
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static DEVICE_API(clock_control, clk_api) = { |
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.get_rate = clk_get_rate |
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}; |
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DEVICE_DT_DEFINE(DT_NODELABEL(clock), NULL, NULL, NULL, NULL, |
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, |
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&clk_api);
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