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131 lines
3.4 KiB
131 lines
3.4 KiB
/* |
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* Copyright (c) 2016 BayLibre, SAS |
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* Copyright (c) 2017 Linaro Ltd |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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* |
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*/ |
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#ifndef ZEPHYR_DRIVERS_I2C_I2C_LL_STM32_H_ |
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#define ZEPHYR_DRIVERS_I2C_I2C_LL_STM32_H_ |
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#include <zephyr/drivers/i2c/stm32.h> |
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#ifdef CONFIG_I2C_STM32_BUS_RECOVERY |
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#include <zephyr/drivers/gpio.h> |
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#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */ |
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#include <zephyr/drivers/dma.h> |
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typedef void (*irq_config_func_t)(const struct device *port); |
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2) |
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/** |
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* @brief structure to convey optional i2c timings settings |
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*/ |
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struct i2c_config_timing { |
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/* i2c peripheral clock in Hz */ |
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uint32_t periph_clock; |
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/* i2c bus speed in Hz */ |
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uint32_t i2c_speed; |
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/* I2C_TIMINGR register value of i2c v2 peripheral */ |
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uint32_t timing_setting; |
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}; |
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#endif |
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#ifdef CONFIG_I2C_STM32_V2_DMA |
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struct stream { |
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const struct device *dev_dma; |
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int32_t dma_channel; |
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}; |
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#endif /* CONFIG_I2C_STM32_V2_DMA */ |
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struct i2c_stm32_config { |
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#ifdef CONFIG_I2C_STM32_INTERRUPT |
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irq_config_func_t irq_config_func; |
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#endif |
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#ifdef CONFIG_I2C_STM32_BUS_RECOVERY |
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struct gpio_dt_spec scl; |
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struct gpio_dt_spec sda; |
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#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */ |
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const struct stm32_pclken *pclken; |
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size_t pclk_len; |
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I2C_TypeDef *i2c; |
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uint32_t bitrate; |
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const struct pinctrl_dev_config *pcfg; |
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2) |
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const struct i2c_config_timing *timings; |
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size_t n_timings; |
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#endif |
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#ifdef CONFIG_I2C_STM32_V2_DMA |
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struct stream tx_dma; |
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struct stream rx_dma; |
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#endif /* CONFIG_I2C_STM32_V2_DMA */ |
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}; |
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struct i2c_stm32_data { |
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#ifdef CONFIG_I2C_STM32_INTERRUPT |
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struct k_sem device_sync_sem; |
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#endif |
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struct k_sem bus_mutex; |
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uint32_t dev_config; |
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2) |
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/* Store the current timing structure set by runtime config */ |
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struct i2c_config_timing current_timing; |
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#endif |
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#ifdef CONFIG_I2C_STM32_V1 |
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uint16_t slave_address; |
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#endif |
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struct { |
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#ifdef CONFIG_I2C_STM32_V1 |
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unsigned int is_restart; |
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unsigned int flags; |
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#endif |
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unsigned int is_write; |
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unsigned int is_arlo; |
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unsigned int is_nack; |
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unsigned int is_err; |
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struct i2c_msg *msg; |
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unsigned int len; |
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uint8_t *buf; |
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} current; |
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#ifdef CONFIG_I2C_TARGET |
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bool master_active; |
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struct i2c_target_config *slave_cfg; |
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#ifdef CONFIG_I2C_STM32_V2 |
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struct i2c_target_config *slave2_cfg; |
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#endif |
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bool slave_attached; |
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#endif |
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bool is_configured; |
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bool smbalert_active; |
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enum i2c_stm32_mode mode; |
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#ifdef CONFIG_SMBUS_STM32_SMBALERT |
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i2c_stm32_smbalert_cb_func_t smbalert_cb_func; |
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const struct device *smbalert_cb_dev; |
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#endif |
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#ifdef CONFIG_I2C_STM32_V2_DMA |
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struct dma_config dma_cfg; |
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struct dma_block_config dma_blk_cfg; |
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#endif /* CONFIG_I2C_STM32_V2_DMA */ |
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}; |
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int stm32_i2c_transaction(const struct device *dev, |
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struct i2c_msg msg, uint8_t *next_msg_flags, |
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uint16_t periph); |
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int stm32_i2c_configure_timing(const struct device *dev, uint32_t clk); |
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int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config); |
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int i2c_stm32_get_config(const struct device *dev, uint32_t *config); |
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void stm32_i2c_event_isr(void *arg); |
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void stm32_i2c_error_isr(void *arg); |
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT |
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void stm32_i2c_combined_isr(void *arg); |
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#endif |
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#ifdef CONFIG_I2C_TARGET |
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int i2c_stm32_target_register(const struct device *dev, struct i2c_target_config *config); |
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int i2c_stm32_target_unregister(const struct device *dev, struct i2c_target_config *config); |
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#endif |
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#endif /* ZEPHYR_DRIVERS_I2C_I2C_LL_STM32_H_ */
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