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295 lines
7.8 KiB
295 lines
7.8 KiB
# XTENSA architecture configuration options |
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# Copyright (c) 2016 Cadence Design Systems, Inc. |
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# SPDX-License-Identifier: Apache-2.0 |
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menu "XTENSA Options" |
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depends on XTENSA |
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config ARCH |
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default "xtensa" |
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config SIMULATOR_XTENSA |
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bool "Simulator Target" |
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help |
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Enable if building to run on simulator. |
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config XTENSA_RESET_VECTOR |
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bool "Build reset vector code" |
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default y |
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help |
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This option controls whether the initial reset vector code is built. |
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This is always needed for the simulator. Real boards may already |
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implement this in boot ROM. |
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config XTENSA_GEN_HANDLERS |
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bool "Automatically generate interrupt handlers" |
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default n |
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help |
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When set, an "xtensa_handlers.h" file is generated |
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containing definitions for the interrupt entry code of the |
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target Xtensa core, based automatically on the details in |
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the core-isa.h file. This replaces the previous scheme |
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where a _soc_inthandlers.h file would be generated offline. |
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config XTENSA_USE_CORE_CRT1 |
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bool "Use crt1.S from core" |
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default y |
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help |
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SoC or boards might define their own __start by setting this setting |
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to false. |
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config XTENSA_ENABLE_BACKTRACE |
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bool "Backtrace on panic exception" |
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default y |
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depends on SOC_SERIES_ESP32 || SOC_FAMILY_INTEL_ADSP || SOC_XTENSA_DC233C |
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help |
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Enable this config option to print backtrace on panic exception |
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config XTENSA_SMALL_VECTOR_TABLE_ENTRY |
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bool "Workaround for small vector table entries" |
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help |
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This option enables a small indirection to bypass the size |
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constraint of the vector table entry and moved the default |
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handlers to the end of vector table, renaming them to |
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_Level\LVL\()VectorHelper. |
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config XTENSA_RPO_CACHE |
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bool "Cached/uncached RPO mapping" |
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help |
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Support Cached/uncached RPO mapping. |
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A design trick on multi-core hardware is to map memory twice |
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so that it can be seen in both (incoherent) cached mappings |
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and a coherent "shared" area. |
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if XTENSA_RPO_CACHE |
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config XTENSA_CACHED_REGION |
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int "Cached RPO mapping" |
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range 0 7 |
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help |
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This specifies which 512M region (0-7, as defined by the Xtensa |
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Region Protection Option) contains the "cached" mapping. |
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config XTENSA_UNCACHED_REGION |
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int "Uncached RPO mapping" |
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range 0 7 |
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help |
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As for XTENSA_CACHED_REGION, this specifies which 512M |
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region (0-7) contains the "uncached" mapping. |
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endif |
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config XTENSA_CCOUNT_HZ |
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int "CCOUNT cycle rate" |
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default 1000000 |
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help |
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Rate in HZ of the Xtensa core as measured by the value of |
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the CCOUNT register. |
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config XTENSA_MORE_SPIN_RELAX_NOPS |
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bool "Use Xtensa specific arch_spin_relax() with more NOPs" |
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help |
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Some Xtensa SoCs, especially under SMP, may need extra |
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NOPs after failure to lock a spinlock. This gives |
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the bus extra time to synchronize the RCW transaction |
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among CPUs. |
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config XTENSA_NUM_SPIN_RELAX_NOPS |
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int "Number of NOPs to be used in arch_spin_relax()" |
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default 1 |
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depends on XTENSA_MORE_SPIN_RELAX_NOPS |
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help |
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Specify the number of NOPs in Xtensa specific |
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arch_spin_relax(). |
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config XTENSA_BREAK_ON_UNRECOVERABLE_EXCEPTIONS |
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bool "Use BREAK instruction on unrecoverable exceptions" |
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help |
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Use BREAK instruction when unrecoverable exceptions are |
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encountered. This requires a debugger attached to catch |
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the BREAK. |
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menu "Xtensa HiFi Options" |
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config XTENSA_CPU_HAS_HIFI |
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bool |
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config XTENSA_CPU_HAS_HIFI3 |
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select XTENSA_CPU_HAS_HIFI |
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bool |
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config XTENSA_CPU_HAS_HIFI4 |
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select XTENSA_CPU_HAS_HIFI |
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bool |
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# Selected when at least one XTENSA_HIFIn version has been configured |
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config XTENSA_HIFI |
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bool |
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if XTENSA_CPU_HAS_HIFI |
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config XTENSA_HIFI3 |
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bool "HiFi3 AudioEngine instructions" |
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depends on XTENSA_CPU_HAS_HIFI3 |
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default y |
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select XTENSA_HIFI |
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help |
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This option enables HiFi 3 instruction support. |
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config XTENSA_HIFI4 |
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bool "HiFi4 AudioEngine instructions" |
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depends on XTENSA_CPU_HAS_HIFI4 |
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default y |
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select XTENSA_HIFI |
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help |
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This option enables HiFi 4 instruction support. |
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config XTENSA_HIFI_SHARING |
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bool "HiFi register sharing" |
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depends on XTENSA_HIFI |
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help |
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This option enables preservation of the hardware HiFi registers |
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across context switches to allow multiple threads to perform |
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concurrent HiFi operations. |
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endif # XTENSA_CPU_HAS_HIFI |
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endmenu # Xtensa HiFi Options |
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config XTENSA_INTERRUPT_NONPREEMPTABLE |
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bool "Xtensa exceptions and interrupts cannot be pre-empted" |
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help |
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Allow use of medium and high priority interrupts without |
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pre-empting low priority interrupts and exceptions. |
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if CPU_HAS_MMU |
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config XTENSA_MMU |
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bool "Xtensa MMU Support" |
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select MMU |
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select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE |
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select KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK if XTENSA_RPO_CACHE |
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select CURRENT_THREAD_USE_NO_TLS if USERSPACE |
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help |
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Enable support for Xtensa Memory Management Unit. |
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if XTENSA_MMU |
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choice |
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prompt "PageTable virtual address" |
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default XTENSA_MMU_PTEVADDR_20000000 |
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help |
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The virtual address for Xtensa page table (PTEVADDR). |
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config XTENSA_MMU_PTEVADDR_20000000 |
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bool "0x20000000" |
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endchoice |
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config XTENSA_MMU_PTEVADDR |
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hex |
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default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000 |
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help |
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The virtual address for Xtensa page table (PTEVADDR). |
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config XTENSA_MMU_PTEVADDR_SHIFT |
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int |
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default 29 if XTENSA_MMU_PTEVADDR_20000000 |
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help |
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The bit shift number for the virtual address for Xtensa |
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page table (PTEVADDR). |
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config XTENSA_MMU_NUM_L1_TABLES |
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int "Number of L1 page tables" |
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default 1 if !USERSPACE |
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default 4 |
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help |
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This option specifies the maximum number of translation tables. |
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Translation tables are directly related to the number of |
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memory domains in the target, considering the kernel itself requires one. |
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config XTENSA_MMU_NUM_L2_TABLES |
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int "Number of L2 page tables" |
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default 20 if USERSPACE |
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default 10 |
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help |
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Each table can address up to 4MB memory address. |
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config XTENSA_MMU_DOUBLE_MAP |
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bool "Map memory in cached and uncached region" |
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help |
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This option specifies that the memory is mapped in two |
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distinct region, cached and uncached. |
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config PRIVILEGED_STACK_SIZE |
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# Must be multiple of CONFIG_MMU_PAGE_SIZE |
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default 4096 |
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config XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP |
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bool "Flush all auto-refill data TLBs when swapping page tables" |
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depends on USERSPACE |
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help |
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This flushes (invalidates) all auto-refill data TLBs when page |
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tables are swapped. |
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endif # XTENSA_MMU |
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endif # CPU_HAS_MMU |
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if CPU_HAS_MPU |
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menuconfig XTENSA_MPU |
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bool "Xtensa MPU Support" |
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select MPU |
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select SRAM_REGION_PERMISSIONS |
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select XTENSA_SMALL_VECTOR_TABLE_ENTRY |
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select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE |
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select CURRENT_THREAD_USE_NO_TLS if USERSPACE |
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select EXPERIMENTAL |
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# TODO: the target the MPU code developed on (basically sample_controller |
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# plus MPU minus s32c1i) does not have cache or SMP capability. |
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# Need to verify functionalities with targets supporting these. |
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depends on !CACHE && !SMP |
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help |
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Enable support for Xtensa Memory Protection Unit. |
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if XTENSA_MPU |
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config XTENSA_MPU_DEFAULT_MEM_TYPE |
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hex "Default Memory Type" |
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default 0x18 |
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help |
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Default memory type for memory regions: non-cacheable memory, |
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non-shareable, non-bufferable and interruptible. |
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If userspace is enabled, it will be used to restore the memory type of |
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the region being removed from a memory domain. |
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config XTENSA_MPU_ONLY_SOC_RANGES |
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bool |
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help |
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Enable this by the SoC to indicate to the architecture code to use |
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the MPU ranges specified by SoC only, and skip the common ranges |
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defined in the core architecture code. This gives total control to |
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the SoC on the MPU ranges. |
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endif # XTENSA_MPU |
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endif # CPU_HAS_MPU |
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config XTENSA_SYSCALL_USE_HELPER |
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bool "Use userspace syscall helper" |
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default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang" |
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depends on (XTENSA_MMU || XTENSA_MPU) && USERSPACE |
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help |
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Use syscall helpers for passing more than 3 arguments. |
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This is a workaround for toolchains where they have |
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issue modeling register usage. |
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config XTENSA_INSECURE_USERSPACE |
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bool |
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default y |
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depends on (XTENSA_MMU || XTENSA_MPU) && USERSPACE |
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endmenu
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