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167 lines
5.1 KiB
167 lines
5.1 KiB
# Kconfig - interrupt controller configuration options |
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# |
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# Copyright (c) 2015 Intel Corporation |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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menu "Interrupt Controllers" |
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menuconfig LOAPIC |
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bool "LOAPIC" |
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depends on X86 |
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help |
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This option selects local APIC as the interrupt controller. |
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if LOAPIC |
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config LOAPIC_BASE_ADDRESS |
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hex "Local APIC Base Address" |
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default 0xFEE00000 |
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help |
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This option specifies the base address of the Local APIC device. |
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config LOAPIC_SPURIOUS_VECTOR |
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bool "Handle LOAPIC spurious interrupts" |
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help |
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A special situation may occur when a processor raises its task |
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priority to be greater than or equal to the level of the |
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interrupt for which the processor INTR signal is currently being |
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asserted. If at the time the INTA cycle is issued, the |
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interrupt that was to be dispensed has become masked (programmed |
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by software), the local APIC will deliver a spurious-interrupt |
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vector. Dispensing the spurious-interrupt vector does not affect |
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the ISR, so the handler for this vector should return without an EOI. |
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From x86 manual Volume 3 Section 10.9. |
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config LOAPIC_SPURIOUS_VECTOR_ID |
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int "LOAPIC spurious vector ID" |
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default -1 |
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depends on LOAPIC_SPURIOUS_VECTOR |
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help |
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IDT vector to use for spurious LOAPIC interrupts. Note that some |
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arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF. |
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If this value is left at -1 the last entry in the IDT will be used. |
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config IOAPIC |
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bool "IO-APIC" |
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default y |
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help |
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This option signifies that the target has an IO-APIC device. This |
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capability allows IO-APIC-dependent code to be included. |
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config IOAPIC_DEBUG |
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bool "IO-APIC Debugging" |
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depends on IOAPIC |
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help |
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Enable debugging for IO-APIC driver. |
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config IOAPIC_NUM_RTES |
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int "Number of Redirection Table Entries available" |
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default 24 |
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depends on IOAPIC |
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help |
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This option indicates the maximum number of Redirection Table Entries |
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(RTEs) (one per IRQ available to the IO-APIC) made available to the |
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kernel, regardless of the number provided by the hardware itself. For |
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most efficient usage of memory, it should match the number of IRQ lines |
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needed by devices connected to the IO-APIC. |
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config IOAPIC_MASK_RTE |
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bool "Mask out RTE entries on boot" |
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default y |
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depends on IOAPIC |
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help |
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At boot, mask all IOAPIC RTEs if they may be in an undefined state. |
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You don't need this if the RTEs are either all guaranteed to be masked |
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when the OS starts up, or a previous boot stage has done some IOAPIC |
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configuration that needs to be preserved. |
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endif #LOAPIC |
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config MVIC |
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bool "Intel Quark D2000 Interrupt Controller (MVIC)" |
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depends on X86 |
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select X86_FIXED_IRQ_MAPPING |
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help |
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The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is |
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configured by default to support 32 external interrupt lines. Unlike the |
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traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and |
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not programmable. In addition, the priorities of these interrupt |
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lines are also fixed. |
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config MVIC_TIMER_IRQ |
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int "IRQ line to use for timer interrupt" |
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range 0 15 |
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default 10 |
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depends on MVIC |
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help |
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Specify the IRQ line to use for the timer interrupt. This should be |
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an IRQ line unused by any hardware. If nested interrupts are enabled, |
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higher interrupt lines have priority. |
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config ARCV2_INTERRUPT_UNIT |
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bool "ARCv2 Interrupt Unit" |
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default y |
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depends on ARC |
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help |
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The ARCv2 interrupt unit has 16 allocated exceptions associated with |
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vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255. |
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The interrupt unit is optional in the ARCv2-based processors. When |
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building a processor, you can configure the processor to include an |
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interrupt unit. The ARCv2 interrupt unit is highly programmable. |
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config PLIC |
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bool "Platform Level Interrupt Controller (PLIC)" |
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default y |
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depends on SOC_FAMILY_RISCV_PRIVILEGE |
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select RISCV_HAS_PLIC |
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help |
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Platform Level Interrupt Controller provides support |
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for external interrupt lines defined by the RISC-V SoC; |
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config DW_ICTL |
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bool "Designware Interrupt Controller" |
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depends on MULTI_LEVEL_INTERRUPTS |
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help |
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Designware Interrupt Controller can be used as a 2nd level interrupt |
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controller which combines several sources of interrupt into one line |
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that is then routed to the 1st level interrupt controller. |
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config DW_ICTL_NAME |
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string "Name for Designware Interrupt Controller" |
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depends on DW_ICTL |
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default "DW_ICTL" |
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help |
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Give a name for the instance of Designware Interrupt Controller |
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config DW_ICTL_OFFSET |
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int "Parent interrupt number to which DW_ICTL maps" |
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default 0 |
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depends on DW_ICTL |
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help |
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Parent interrupt number to which DW_ICTL maps |
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config DW_ISR_TBL_OFFSET |
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int "Offset in the SW ISR Table" |
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default 0 |
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depends on DW_ICTL |
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help |
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This indicates the offset in the SW_ISR_TABLE beginning from where |
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the ISRs for Designware Interrupt Controller are assigned. |
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config DW_ICTL_INIT_PRIORITY |
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int "Init priority for DW interrupt controller" |
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default 60 |
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depends on DW_ICTL |
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help |
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DesignWare Interrupt Controller initialization priority. |
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source "drivers/interrupt_controller/Kconfig.stm32" |
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source "drivers/interrupt_controller/Kconfig.multilevel" |
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source "drivers/interrupt_controller/Kconfig.s1000" |
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source "drivers/interrupt_controller/Kconfig.rv32m1" |
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endmenu
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