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118 lines
3.4 KiB
118 lines
3.4 KiB
.. _scobc_module1: |
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Space Cubics OBC module 1 |
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######################### |
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Overview |
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`Space Cubics`_ OBC module 1 is a single board computer for spacecraft, |
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especially for 3U CubeSats. The board is based on Xilinx Artix-7 FPGA and |
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implements ARM Cortex M3 as the main CPU. |
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.. figure:: scobc.jpg |
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:align: center |
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:alt: Space Cubics OBC module 1 |
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Space Cubics OBC module 1 |
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It is designed to survive in the severe space environment, extreme temperature, |
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vacuum, and space radiation. |
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As the name suggests, the board form factor is a module and requires a base I/O |
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board connected at CON1, a board-to-board connector. This modularity allows |
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CubeSat designers the freedom to connect and expand the capability required for |
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their mission. |
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Hardware |
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Supported Features |
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================== |
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The Space Cubics OBC module 1 provides the following hardware features: |
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+-----------+------------+------------------------------------+ |
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| Interface | Controller | Driver/Component | |
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+===========+============+====================================+ |
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| NVIC | on-chip | nested vector interrupt controller | |
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+-----------+------------+------------------------------------+ |
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| SYSTICK | on-chip | systick | |
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+-----------+------------+------------------------------------+ |
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| UART | on-chip | serial port-polling; | |
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| | | serial port-interrupt | |
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+-----------+------------+------------------------------------+ |
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The default configuration for the board can be found in the defconfig file: |
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:file:`boards/arm/scobc_module1/scobc_module1_defconfig`. |
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Other hardware features are not currently supported by the port. |
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System Clock |
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============ |
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The board has two 24 MHz external oscillators connected to the FPGA for |
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redundancy. The FPGA will select an active oscillator as CPU system clock. The |
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selected clock signal is then used by the CMT in the FPGA, and drives the CPU at |
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48 MHz by default. |
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Serial Port |
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=========== |
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The default configuration contains one SC UART IP, which is register compatible |
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with Xilinx UART Lite for basic TX and RX. This UART is configured as the |
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default console and is accessible through the CON1 pin 43 and 45 for Rx and Tx, |
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respectively. |
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Programming and Debugging |
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************************* |
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Flashing |
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======== |
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Here is an example for building and flashing the \`hello\_world\` |
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application for the board: |
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Here is an example for building and flashing the :ref:`hello_world` application |
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for the default design: |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: scobc_module1 |
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:goals: flash |
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After flashing, you should see message similar to the following in the terminal: |
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.. code-block:: console |
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*** Booting Zephyr OS build zephyr-v2.7.99 *** |
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Hello World! scobc_module1 |
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Note, however, that the application was not persisted in flash memory by the |
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above steps. It was merely written to internal RAM in the FPGA. |
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Debugging |
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========= |
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Here is an example for the :ref:`hello_world` application. |
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.. zephyr-app-commands:: |
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:zephyr-app: samples/hello_world |
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:board: scobc_module1 |
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:goals: debug |
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Step through the application in your debugger, and you should see a message |
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similar to the following in the terminal: |
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.. code-block:: console |
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*** Booting Zephyr OS build zephyr-v2.7.99 *** |
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Hello World! scobc_module1 |
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References |
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********** |
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.. target-notes:: |
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.. _Space Cubics: |
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https://spacecubics.com/
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