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Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
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zephyr/dts/vendor/nordic/nrf9280.dtsi

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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <nordic/nrf_common.dtsi>
#include <zephyr/dt-bindings/adc/nrf-saadc-haltium.h>
#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h>
#include <zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h>
#include <zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h>
#include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
/delete-node/ &sw_pwm;
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpuapp: cpu@2 {
compatible = "arm,cortex-m33";
reg = <2>;
device_type = "cpu";
clock-frequency = <DT_FREQ_M(320)>;
};
cpurad: cpu@3 {
compatible = "arm,cortex-m33";
reg = <3>;
device_type = "cpu";
clock-frequency = <DT_FREQ_M(256)>;
};
cpuppr: cpu@d {
compatible = "nordic,vpr";
reg = <13>;
device_type = "cpu";
clock-frequency = <DT_FREQ_M(16)>;
riscv,isa = "rv32emc";
nordic,bus-width = <32>;
cpuppr_vevif_rx: mailbox {
compatible = "nordic,nrf-vevif-task-rx";
status = "disabled";
interrupt-parent = <&cpuppr_clic>;
interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>,
<1 NRF_DEFAULT_IRQ_PRIORITY>,
<2 NRF_DEFAULT_IRQ_PRIORITY>,
<3 NRF_DEFAULT_IRQ_PRIORITY>,
<4 NRF_DEFAULT_IRQ_PRIORITY>,
<5 NRF_DEFAULT_IRQ_PRIORITY>,
<6 NRF_DEFAULT_IRQ_PRIORITY>,
<7 NRF_DEFAULT_IRQ_PRIORITY>,
<8 NRF_DEFAULT_IRQ_PRIORITY>,
<9 NRF_DEFAULT_IRQ_PRIORITY>,
<10 NRF_DEFAULT_IRQ_PRIORITY>,
<11 NRF_DEFAULT_IRQ_PRIORITY>,
<12 NRF_DEFAULT_IRQ_PRIORITY>,
<13 NRF_DEFAULT_IRQ_PRIORITY>,
<14 NRF_DEFAULT_IRQ_PRIORITY>,
<15 NRF_DEFAULT_IRQ_PRIORITY>;
#mbox-cells = <1>;
nordic,tasks = <16>;
nordic,tasks-mask = <0x0000fff0>;
};
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
suit_storage_partition: memory@e6b7000 {
reg = <0xe6b7000 DT_SIZE_K(40)>;
};
};
clocks {
hfxo: hfxo {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <DT_FREQ_M(32)>;
};
fll16m: fll16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <DT_FREQ_M(16)>;
};
hsfll120: hsfll120 {
compatible = "nordic,nrf-hsfll-global";
clocks = <&fll16m>;
#clock-cells = <0>;
clock-frequency = <320000000>;
supported-clock-frequencies = <64000000
128000000
256000000
320000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
mram1x: mram@e000000 {
compatible = "nordic,mram";
reg = <0xe000000 DT_SIZE_K(8192)>;
erase-block-size = <4096>;
write-block-size = <16>;
};
cpuapp_uicr: uicr@fff8000 {
compatible = "nordic,nrf-uicr-v2";
reg = <0xfff8000 DT_SIZE_K(2)>;
domain = <2>;
};
cpurad_uicr: uicr@fffa000 {
compatible = "nordic,nrf-uicr-v2";
reg = <0xfffa000 DT_SIZE_K(2)>;
domain = <3>;
};
ficr: ficr@fffe000 {
compatible = "nordic,nrf-ficr";
reg = <0xfffe000 DT_SIZE_K(2)>;
#nordic,ficr-cells = <1>;
};
cpuapp_ram0: sram@22000000 {
compatible = "mmio-sram";
reg = <0x22000000 DT_SIZE_K(32)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x22000000 0x8000>;
};
cpurad_ram0: sram@23000000 {
compatible = "mmio-sram";
reg = <0x23000000 DT_SIZE_K(192)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x23000000 0x30000>;
};
cpurad_ram1: sram@23040000 {
compatible = "mmio-sram";
reg = <0x23040000 DT_SIZE_K(32)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x23040000 0x8000>;
};
cpuapp_peripherals: peripheral@52000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x52000000 0x1000000>;
cpuapp_hsfll: clock@d000 {
compatible = "nordic,nrf-hsfll-local";
#clock-cells = <0>;
reg = <0xd000 0x1000>;
clocks = <&fll16m>;
clock-frequency = <DT_FREQ_M(320)>;
nordic,ficrs =
<&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>,
<&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>,
<&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>;
nordic,ficr-names = "vsup", "coarse", "fine";
};
cpuapp_ipct: ipct@13000 {
compatible = "nordic,nrf-ipct-local";
reg = <0x13000 0x1000>;
status = "disabled";
channels = <4>;
interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>,
<65 NRF_DEFAULT_IRQ_PRIORITY>;
};
cpuapp_wdt010: watchdog@14000 {
compatible = "nordic,nrf-wdt";
reg = <0x14000 0x1000>;
status = "disabled";
interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>;
};
cpuapp_wdt011: watchdog@15000 {
compatible = "nordic,nrf-wdt";
reg = <0x15000 0x1000>;
status = "disabled";
interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>;
};
cpuapp_ieee802154: ieee802154 {
compatible = "nordic,nrf-ieee802154";
status = "disabled";
};
cpuapp_resetinfo: resetinfo@1e000 {
compatible = "nordic,nrf-resetinfo";
reg = <0x1e000 0x1000>;
};
};
cpurad_peripherals: peripheral@53000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53000000 0x1000000>;
cpurad_hsfll: clock@d000 {
compatible = "nordic,nrf-hsfll-local";
#clock-cells = <0>;
reg = <0xd000 0x1000>;
clocks = <&fll16m>;
clock-frequency = <DT_FREQ_M(256)>;
nordic,ficrs =
<&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>,
<&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>,
<&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>;
nordic,ficr-names = "vsup", "coarse", "fine";
};
cpurad_wdt010: watchdog@13000 {
compatible = "nordic,nrf-wdt";
reg = <0x13000 0x1000>;
status = "disabled";
interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>;
};
cpurad_wdt011: watchdog@14000 {
compatible = "nordic,nrf-wdt";
reg = <0x14000 0x1000>;
status = "disabled";
interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>;
};
cpurad_resetinfo: resetinfo@1e000 {
compatible = "nordic,nrf-resetinfo";
reg = <0x1e000 0x1000>;
};
dppic020: dppic@22000 {
compatible = "nordic,nrf-dppic-local";
reg = <0x22000 0x1000>;
status = "disabled";
};
cpurad_ipct: ipct@24000 {
compatible = "nordic,nrf-ipct-local";
reg = <0x24000 0x1000>;
status = "disabled";
channels = <8>;
interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>,
<65 NRF_DEFAULT_IRQ_PRIORITY>;
};
egu020: egu@25000 {
compatible = "nordic,nrf-egu";
reg = <0x25000 0x1000>;
status = "disabled";
interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>;
};
timer020: timer@28000 {
compatible = "nordic,nrf-timer";
reg = <0x28000 0x1000>;
status = "disabled";
cc-num = <8>;
interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
clocks = <&hfxo>;
prescaler = <0>;
};
timer021: timer@29000 {
compatible = "nordic,nrf-timer";
reg = <0x29000 0x1000>;
status = "disabled";
cc-num = <8>;
interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
clocks = <&hfxo>;
prescaler = <0>;
};
timer022: timer@2a000 {
compatible = "nordic,nrf-timer";
reg = <0x2a000 0x1000>;
status = "disabled";
cc-num = <8>;
interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
clocks = <&hfxo>;
prescaler = <0>;
};
rtc: rtc@2b000 {
compatible = "nordic,nrf-rtc";
reg = <0x2b000 0x1000>;
status = "disabled";
cc-num = <4>;
clock-frequency = <32768>;
interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <1>;
};
radio: radio@2c000 {
compatible = "nordic,nrf-radio";
reg = <0x2c000 0x1000>;
status = "disabled";
ble-2mbps-supported;
ble-coded-phy-supported;
dfe-supported;
ieee802154-supported;
interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>;
cpurad_ieee802154: ieee802154 {
compatible = "nordic,nrf-ieee802154";
status = "disabled";
};
};
ccm030: ccm@3a000 {
compatible = "nordic,nrf-ccm";
reg = <0x3a000 0x1000>;
interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
ecb030: ecb@3b000 {
compatible = "nordic,nrf-ecb";
reg = <0x3b000 0x1000>;
interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
ccm031: ccm@3c000 {
compatible = "nordic,nrf-ccm";
reg = <0x3c000 0x1000>;
interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
ecb031: ecb@3d000 {
compatible = "nordic,nrf-ecb";
reg = <0x3d000 0x1000>;
status = "disabled";
interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>;
};
};
global_peripherals: peripheral@5f000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5f000000 0x1000000>;
usbhs: usbhs@86000 {
compatible = "nordic,nrf-usbhs", "snps,dwc2";
reg = <0x86000 0x1000>, <0x2f700000 0x40000>;
reg-names = "wrapper", "core";
interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>;
num-in-eps = <8>;
num-out-eps = <10>;
ghwcfg1 = <0xaa555000>;
ghwcfg2 = <0x22abfc72>;
ghwcfg4 = <0x1e10aa60>;
status = "disabled";
};
exmif: exmif@95000 {
compatible = "nordic,nrf-exmif", "snps,designware-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x95000 0x500 0x95500 0xb00>;
reg-names = "wrapper", "core";
interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>;
clock-frequency = <DT_FREQ_M(400)>;
fifo-depth = <32>;
status = "disabled";
};
cpusec_bellboard: mailbox@99000 {
reg = <0x99000 0x1000>;
status = "disabled";
#mbox-cells = <1>;
};
cpuapp_bellboard: mailbox@9a000 {
reg = <0x9a000 0x1000>;
status = "disabled";
#mbox-cells = <1>;
};
cpurad_bellboard: mailbox@9b000 {
reg = <0x9b000 0x1000>;
status = "disabled";
#mbox-cells = <1>;
};
cpucell_bellboard: mailbox@9c000 {
reg = <0x9c000 0x1000>;
status = "disabled";
#mbox-cells = <1>;
};
canpll: clock-controller@8c2000{
compatible = "nordic,nrf-auxpll";
reg = <0x8c2000 0x1000>;
interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>;
clocks = <&hfxo>;
#clock-cells = <0>;
nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>;
nordic,frequency = <0>;
nordic,out-div = <2>;
nordic,out-drive = <0>;
nordic,current-tune = <6>;
nordic,sdm-disable;
nordic,range = "high";
status = "disabled";
};
cpusys_vevif_tx: mailbox@8c8000 {
compatible = "nordic,nrf-vevif-task-tx";
reg = <0x8c8000 0x1000>;
status = "disabled";
#mbox-cells = <1>;
nordic,tasks = <32>;
nordic,tasks-mask = <0xfffff0ff>;
};
ipct120: ipct@8d1000 {
compatible = "nordic,nrf-ipct-global";
reg = <0x8d1000 0x1000>;
status = "disabled";
channels = <8>;
global-domain-id = <12>;
};
dppic120: dppic@8e1000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x8e1000 0x1000>;
status = "disabled";
};
timer120: timer@8e2000 {
compatible = "nordic,nrf-timer";
reg = <0x8e2000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
clocks = <&hsfll120>;
prescaler = <0>;
};
timer121: timer@8e3000 {
compatible = "nordic,nrf-timer";
reg = <0x8e3000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
clocks = <&hsfll120>;
prescaler = <0>;
};
pwm120: pwm@8e4000 {
compatible = "nordic,nrf-pwm";
reg = <0x8e4000 0x1000>;
status = "disabled";
interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
};
spi120: spi@8e6000 {
compatible = "nordic,nrf-spim";
reg = <0x8e6000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(32)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_SCK>;
};
uart120: uart@8e6000 {
compatible = "nordic,nrf-uarte";
reg = <0x8e6000 0x1000>;
status = "disabled";
interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>;
endtx-stoptx-supported;
frame-timeout-supported;
};
spi121: spi@8e7000 {
compatible = "nordic,nrf-spim";
reg = <0x8e7000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(32)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_SCK>;
};
cpuppr_vpr: vpr@908000 {
compatible = "nordic,nrf-vpr-coprocessor";
reg = <0x908000 0x1000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x908000 0x1000>;
cpuppr_vevif_tx: mailbox@0 {
compatible = "nordic,nrf-vevif-task-tx";
reg = <0x0 0x1000>;
status = "disabled";
#mbox-cells = <1>;
nordic,tasks = <16>;
nordic,tasks-mask = <0x0000fff0>;
};
};
ipct130: ipct@921000 {
compatible = "nordic,nrf-ipct-global";
reg = <0x921000 0x1000>;
status = "disabled";
channels = <8>;
global-domain-id = <13>;
};
dppic130: dppic@922000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x922000 0x1000>;
status = "disabled";
};
rtc130: rtc@928000 {
compatible = "nordic,nrf-rtc";
reg = <0x928000 0x1000>;
status = "disabled";
cc-num = <4>;
clock-frequency = <32768>;
interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <1>;
};
rtc131: rtc@929000 {
compatible = "nordic,nrf-rtc";
reg = <0x929000 0x1000>;
status = "disabled";
cc-num = <4>;
clock-frequency = <32768>;
interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>;
prescaler = <1>;
};
wdt131: watchdog@92b000 {
compatible = "nordic,nrf-wdt";
reg = <0x92b000 0x1000>;
status = "disabled";
interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>;
};
wdt132: watchdog@92c000 {
compatible = "nordic,nrf-wdt";
reg = <0x92c000 0x1000>;
status = "disabled";
interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>;
};
gpiote130: gpiote@934000 {
compatible = "nordic,nrf-gpiote";
reg = <0x934000 0x1000>;
status = "disabled";
instance = <130>;
};
gpiote131: gpiote@935000 {
compatible = "nordic,nrf-gpiote";
reg = <0x935000 0x1000>;
status = "disabled";
instance = <131>;
};
gpio0: gpio@938000 {
compatible = "nordic,nrf-gpio";
reg = <0x938000 0x200>;
status = "disabled";
#gpio-cells = <2>;
gpio-controller;
gpiote-instance = <&gpiote130>;
ngpios = <13>;
port = <0>;
};
gpio1: gpio@938200 {
compatible = "nordic,nrf-gpio";
reg = <0x938200 0x200>;
status = "disabled";
#gpio-cells = <2>;
gpio-controller;
gpiote-instance = <&gpiote130>;
ngpios = <12>;
port = <1>;
};
gpio2: gpio@938400 {
compatible = "nordic,nrf-gpio";
reg = <0x938400 0x200>;
status = "disabled";
#gpio-cells = <2>;
gpio-controller;
gpiote-instance = <&gpiote130>;
ngpios = <12>;
port = <2>;
};
gpio6: gpio@938c00 {
compatible = "nordic,nrf-gpio";
reg = <0x938c00 0x200>;
status = "disabled";
#gpio-cells = <2>;
gpio-controller;
ngpios = <14>;
port = <6>;
};
gpio8: gpio@939000 {
compatible = "nordic,nrf-gpio";
reg = <0x939000 0x200>;
status = "disabled";
#gpio-cells = <2>;
gpio-controller;
ngpios = <5>;
port = <8>;
};
gpio9: gpio@939200 {
compatible = "nordic,nrf-gpio";
reg = <0x939200 0x200>;
status = "disabled";
#gpio-cells = <2>;
gpio-controller;
gpiote-instance = <&gpiote130>;
ngpios = <6>;
port = <9>;
};
gpio11: gpio@939600 {
compatible = "nordic,nrf-gpio";
reg = <0x939600 0x200>;
status = "disabled";
#gpio-cells = <2>;
gpio-controller;
gpiote-instance = <&gpiote131>;
ngpios = <8>;
port = <11>;
};
dppic131: dppic@981000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x981000 0x1000>;
status = "disabled";
};
adc: adc@982000 {
compatible = "nordic,nrf-saadc";
reg = <0x982000 0x1000>;
interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
#io-channel-cells = <1>;
zephyr,pm-device-runtime-auto;
};
comp: comparator@983000 {
/*
* Use compatible "nordic,nrf-comp" to configure as COMP
* Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
*/
compatible = "nordic,nrf-comp";
reg = <0x983000 0x1000>;
status = "disabled";
interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>;
};
temp: temperature-sensor@984000 {
compatible = "nordic,nrf-temp";
reg = <0x984000 0x1000>;
interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>;
status = "disabled";
};
dppic132: dppic@991000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x991000 0x1000>;
status = "disabled";
};
qdec130: qdec@994000 {
compatible = "nordic,nrf-qdec";
reg = <0x994000 0x1000>;
status = "disabled";
interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>;
};
qdec131: qdec@995000 {
compatible = "nordic,nrf-qdec";
reg = <0x995000 0x1000>;
status = "disabled";
interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>;
};
grtc: grtc@99c000 {
compatible = "nordic,nrf-grtc";
reg = <0x99c000 0x1000>;
status = "disabled";
cc-num = <16>;
};
dppic133: dppic@9a1000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x9a1000 0x1000>;
status = "disabled";
};
timer130: timer@9a2000 {
compatible = "nordic,nrf-timer";
reg = <0x9a2000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
timer131: timer@9a3000 {
compatible = "nordic,nrf-timer";
reg = <0x9a3000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
pwm130: pwm@9a4000 {
compatible = "nordic,nrf-pwm";
reg = <0x9a4000 0x1000>;
status = "disabled";
interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
};
i2c130: i2c@9a5000 {
compatible = "nordic,nrf-twim";
reg = <0x9a5000 0x1000>;
status = "disabled";
interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi130: spi@9a5000 {
compatible = "nordic,nrf-spim";
reg = <0x9a5000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart130: uart@9a5000 {
compatible = "nordic,nrf-uarte";
reg = <0x9a5000 0x1000>;
status = "disabled";
interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
i2c131: i2c@9a6000 {
compatible = "nordic,nrf-twim";
reg = <0x9a6000 0x1000>;
status = "disabled";
interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi131: spi@9a6000 {
compatible = "nordic,nrf-spim";
reg = <0x9a6000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart131: uart@9a6000 {
compatible = "nordic,nrf-uarte";
reg = <0x9a6000 0x1000>;
status = "disabled";
interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
dppic134: dppic@9b1000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x9b1000 0x1000>;
status = "disabled";
};
timer132: timer@9b2000 {
compatible = "nordic,nrf-timer";
reg = <0x9b2000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
timer133: timer@9b3000 {
compatible = "nordic,nrf-timer";
reg = <0x9b3000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
pwm131: pwm@9b4000 {
compatible = "nordic,nrf-pwm";
reg = <0x9b4000 0x1000>;
status = "disabled";
interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
};
i2c132: i2c@9b5000 {
compatible = "nordic,nrf-twim";
reg = <0x9b5000 0x1000>;
status = "disabled";
interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi132: spi@9b5000 {
compatible = "nordic,nrf-spim";
reg = <0x9b5000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart132: uart@9b5000 {
compatible = "nordic,nrf-uarte";
reg = <0x9b5000 0x1000>;
status = "disabled";
interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
i2c133: i2c@9b6000 {
compatible = "nordic,nrf-twim";
reg = <0x9b6000 0x1000>;
status = "disabled";
interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi133: spi@9b6000 {
compatible = "nordic,nrf-spim";
reg = <0x9b6000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart133: uart@9b6000 {
compatible = "nordic,nrf-uarte";
reg = <0x9b6000 0x1000>;
status = "disabled";
interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
dppic135: dppic@9c1000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x9c1000 0x1000>;
status = "disabled";
};
timer134: timer@9c2000 {
compatible = "nordic,nrf-timer";
reg = <0x9c2000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
timer135: timer@9c3000 {
compatible = "nordic,nrf-timer";
reg = <0x9c3000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
pwm132: pwm@9c4000 {
compatible = "nordic,nrf-pwm";
reg = <0x9c4000 0x1000>;
status = "disabled";
interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
};
i2c134: i2c@9c5000 {
compatible = "nordic,nrf-twim";
reg = <0x9c5000 0x1000>;
status = "disabled";
interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi134: spi@9c5000 {
compatible = "nordic,nrf-spim";
reg = <0x9c5000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart134: uart@9c5000 {
compatible = "nordic,nrf-uarte";
reg = <0x9c5000 0x1000>;
status = "disabled";
interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
i2c135: i2c@9c6000 {
compatible = "nordic,nrf-twim";
reg = <0x9c6000 0x1000>;
status = "disabled";
interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi135: spi@9c6000 {
compatible = "nordic,nrf-spim";
reg = <0x9c6000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart135: uart@9c6000 {
compatible = "nordic,nrf-uarte";
reg = <0x9c6000 0x1000>;
status = "disabled";
interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
dppic136: dppic@9d1000 {
compatible = "nordic,nrf-dppic-global";
reg = <0x9d1000 0x1000>;
status = "disabled";
};
timer136: timer@9d2000 {
compatible = "nordic,nrf-timer";
reg = <0x9d2000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
timer137: timer@9d3000 {
compatible = "nordic,nrf-timer";
reg = <0x9d3000 0x1000>;
status = "disabled";
cc-num = <6>;
interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>;
max-bit-width = <32>;
prescaler = <0>;
};
pwm133: pwm@9d4000 {
compatible = "nordic,nrf-pwm";
reg = <0x9d4000 0x1000>;
status = "disabled";
interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>;
#pwm-cells = <3>;
};
i2c136: i2c@9d5000 {
compatible = "nordic,nrf-twim";
reg = <0x9d5000 0x1000>;
status = "disabled";
interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi136: spi@9d5000 {
compatible = "nordic,nrf-spim";
reg = <0x9d5000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart136: uart@9d5000 {
compatible = "nordic,nrf-uarte";
reg = <0x9d5000 0x1000>;
status = "disabled";
interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
i2c137: i2c@9d6000 {
compatible = "nordic,nrf-twim";
reg = <0x9d6000 0x1000>;
status = "disabled";
interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
easydma-maxcnt-bits = <15>;
#address-cells = <1>;
#size-cells = <0>;
nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>,
<NRF_FUN_TWIM_SCL>;
zephyr,pm-device-runtime-auto;
};
spi137: spi@9d6000 {
compatible = "nordic,nrf-spim";
reg = <0x9d6000 0x1000>;
status = "disabled";
easydma-maxcnt-bits = <15>;
interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
max-frequency = <DT_FREQ_M(8)>;
#address-cells = <1>;
#size-cells = <0>;
rx-delay-supported;
rx-delay = <1>;
nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>,
<NRF_FUN_SPIM_SCK>,
<NRF_FUN_SPIS_MISO>,
<NRF_FUN_SPIS_SCK>;
};
uart137: uart@9d6000 {
compatible = "nordic,nrf-uarte";
reg = <0x9d6000 0x1000>;
status = "disabled";
interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>;
nordic,clockpin-enable = <NRF_FUN_UART_TX>;
endtx-stoptx-supported;
frame-timeout-supported;
};
};
};
cpuapp_ppb: cpuapp-ppb-bus {
#address-cells = <1>;
#size-cells = <1>;
cpuapp_systick: timer@e000e010 {
compatible = "arm,armv8m-systick";
reg = <0xe000e010 0x10>;
status = "disabled";
};
cpuapp_nvic: interrupt-controller@e000e100 {
compatible = "arm,v8m-nvic";
reg = <0xe000e100 0xc00>;
arm,num-irq-priority-bits = <3>;
#interrupt-cells = <2>;
interrupt-controller;
#address-cells = <1>;
};
};
cpurad_ppb: cpurad-ppb-bus {
#address-cells = <1>;
#size-cells = <1>;
cpurad_systick: timer@e000e010 {
compatible = "arm,armv8m-systick";
reg = <0xe000e010 0x10>;
status = "disabled";
};
cpurad_nvic: interrupt-controller@e000e100 {
compatible = "arm,v8m-nvic";
reg = <0xe000e100 0xc00>;
arm,num-irq-priority-bits = <3>;
#interrupt-cells = <2>;
interrupt-controller;
#address-cells = <1>;
};
};
cpuppr_private: cpuppr-private-bus {
#address-cells = <1>;
#size-cells = <1>;
cpuppr_clic: interrupt-controller@5f909000 {
compatible = "nordic,nrf-clic";
reg = <0x5f909000 0x3000>;
status = "disabled";
#interrupt-cells = <2>;
interrupt-controller;
#address-cells = <1>;
};
};
temp_nrfs: temp {
compatible = "nordic,nrf-temp-nrfs";
status = "disabled";
};
};