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363 lines
11 KiB
363 lines
11 KiB
/* |
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* Copyright (c) 2024-2025 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT renesas_ra_gpio_ioport |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h> |
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#include <zephyr/drivers/misc/renesas_ra_external_interrupt/renesas_ra_external_interrupt.h> |
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#include <zephyr/drivers/gpio/gpio_utils.h> |
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#include <soc.h> |
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struct gpio_ra_irq_info { |
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const struct device *port_irq; |
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const uint8_t *const pins; |
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size_t num; |
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}; |
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struct gpio_ra_config { |
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struct gpio_driver_config common; |
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uint8_t port_num; |
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R_PORT0_Type *port; |
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const struct gpio_ra_irq_info *irq_info; |
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const size_t irq_info_size; |
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gpio_pin_t vbatt_pins[]; |
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}; |
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struct gpio_ra_data { |
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struct gpio_driver_data common; |
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sys_slist_t callbacks; |
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}; |
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#if CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT |
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static const struct gpio_ra_irq_info *query_irq_info(const struct device *dev, uint32_t pin) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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for (int i = 0; i < config->irq_info_size; i++) { |
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const struct gpio_ra_irq_info *info = &config->irq_info[i]; |
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for (int j = 0; j < info->num; j++) { |
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if (info->pins[j] == pin) { |
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return info; |
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} |
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} |
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} |
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return NULL; |
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} |
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static void gpio_ra_callback_adapter(const struct device *dev, gpio_pin_t pin) |
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{ |
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struct gpio_ra_data *data = dev->data; |
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gpio_fire_callbacks(&data->callbacks, dev, BIT(pin)); |
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} |
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#endif |
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static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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struct ra_pinctrl_soc_pin pincfg; |
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uint32_t pfs_cfg; |
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if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) { |
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return -ENOTSUP; |
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} |
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if ((flags & GPIO_PULL_DOWN) != 0U) { |
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return -ENOTSUP; |
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} |
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if (!IS_ENABLED(CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT) && ((flags & GPIO_INT_ENABLE) != 0)) { |
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return -ENOTSUP; |
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} |
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#if CONFIG_GPIO_RA_HAS_VBTICTLR |
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if (config->vbatt_pins[0] != 0xFF) { |
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uint32_t clear = 0; |
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for (int i = 0; config->vbatt_pins[i] != '\0'; i++) { |
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if (config->vbatt_pins[i] == pin) { |
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WRITE_BIT(clear, i, 1); |
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} |
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} |
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); |
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R_SYSTEM->VBTICTLR &= (uint8_t)~clear; |
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); |
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} |
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#endif |
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pincfg.port_num = config->port_num; |
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pincfg.pin_num = pin; |
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/* Initial pin settings when PFS is zeroed: |
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* - Low output, input mode |
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* - Pull-up disabled, CMOS output |
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* - Low drive strength |
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* - Not used for IRQ or analog |
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* - Configured as general I/O |
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*/ |
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pfs_cfg = 0; |
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if ((flags & GPIO_OUTPUT) != 0U) { |
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/* Set output pin initial value */ |
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { |
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WRITE_BIT(pfs_cfg, R_PFS_PORT_PIN_PmnPFS_PODR_Pos, 1); |
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} |
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WRITE_BIT(pfs_cfg, R_PFS_PORT_PIN_PmnPFS_PDR_Pos, 1); |
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} |
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if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) { |
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WRITE_BIT(pfs_cfg, R_PFS_PORT_PIN_PmnPFS_NCODR_Pos, 1); |
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} |
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if ((flags & GPIO_PULL_UP) != 0) { |
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WRITE_BIT(pfs_cfg, R_PFS_PORT_PIN_PmnPFS_PCR_Pos, 1); |
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} |
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#if CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT |
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if ((flags & GPIO_INT_ENABLE) != 0) { |
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const struct gpio_ra_irq_info *irq_info = query_irq_info(dev, pin); |
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int err = 0; |
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if (irq_info == NULL) { |
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return -EINVAL; |
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} |
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if (!device_is_ready(irq_info->port_irq)) { |
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return -EWOULDBLOCK; |
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} |
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struct gpio_ra_callback callback = { |
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.port = (struct device *)dev, |
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.port_num = config->port_num, |
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.pin = pin, |
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.mode = flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE), |
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.trigger = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1), |
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.isr = gpio_ra_callback_adapter, |
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}; |
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err = gpio_ra_interrupt_set(irq_info->port_irq, &callback); |
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if (err < 0) { |
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return err; |
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} |
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WRITE_BIT(pfs_cfg, R_PFS_PORT_PIN_PmnPFS_ISEL_Pos, 1); |
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} |
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if ((flags & GPIO_INT_DISABLE) != 0) { |
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const struct gpio_ra_irq_info *irq_info = query_irq_info(dev, pin); |
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if (irq_info == NULL) { |
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return -EINVAL; |
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} |
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if (!device_is_ready(irq_info->port_irq)) { |
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return -EWOULDBLOCK; |
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} |
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gpio_ra_interrupt_unset(irq_info->port_irq, config->port_num, pin); |
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WRITE_BIT(pfs_cfg, R_PFS_PORT_PIN_PmnPFS_ISEL_Pos, 0); |
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} |
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#endif |
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pincfg.cfg = |
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pfs_cfg | (((flags & RENESAS_GPIO_DS_MSK) >> 8) << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos); |
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return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE); |
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} |
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__maybe_unused static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, |
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gpio_flags_t *flags) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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uint32_t pincfg; |
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if (pin >= RA_PINCTRL_PIN_NUM) { |
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return -EINVAL; |
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} |
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memset(flags, 0, sizeof(gpio_flags_t)); |
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pincfg = R_PFS->PORT[config->port_num].PIN[pin].PmnPFS; |
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if (pincfg & BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos)) { |
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*flags |= GPIO_OUTPUT; |
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} else { |
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*flags |= GPIO_INPUT; |
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} |
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if (pincfg & BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos)) { |
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*flags |= GPIO_LINE_OPEN_DRAIN; |
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} |
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if (pincfg & BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos)) { |
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*flags |= GPIO_PULL_UP; |
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} |
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return 0; |
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} |
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static int gpio_ra_port_get_raw(const struct device *dev, uint32_t *value) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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R_PORT0_Type *port = config->port; |
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*value = port->PIDR; |
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return 0; |
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} |
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static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, |
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gpio_port_value_t value) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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R_PORT0_Type *port = config->port; |
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port->PODR = ((port->PODR & ~mask) | (value & mask)); |
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return 0; |
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} |
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static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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R_PORT0_Type *port = config->port; |
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port->PODR = (port->PODR | pins); |
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return 0; |
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} |
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static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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R_PORT0_Type *port = config->port; |
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port->PODR = (port->PODR & ~pins); |
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return 0; |
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} |
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static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) |
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{ |
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const struct gpio_ra_config *config = dev->config; |
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R_PORT0_Type *port = config->port; |
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port->PODR = (port->PODR ^ pins); |
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return 0; |
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} |
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#if CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT |
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static int gpio_ra_pin_interrupt_configure(const struct device *port, gpio_pin_t pin, |
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enum gpio_int_mode mode, enum gpio_int_trig trig) |
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{ |
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gpio_flags_t flags; |
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int err; |
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err = gpio_ra_pin_get_config(port, pin, &flags); |
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if (err) { |
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return err; |
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} |
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return gpio_ra_pin_configure(port, pin, (flags | mode | trig)); |
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} |
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static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callback *callback, |
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bool set) |
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{ |
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struct gpio_ra_data *data = dev->data; |
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return gpio_manage_callback(&data->callbacks, callback, set); |
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} |
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#endif |
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static DEVICE_API(gpio, gpio_ra_drv_api_funcs) = { |
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.pin_configure = gpio_ra_pin_configure, |
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#ifdef CONFIG_GPIO_GET_CONFIG |
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.pin_get_config = gpio_ra_pin_get_config, |
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#endif |
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.port_get_raw = gpio_ra_port_get_raw, |
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.port_set_masked_raw = gpio_ra_port_set_masked_raw, |
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.port_set_bits_raw = gpio_ra_port_set_bits_raw, |
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.port_clear_bits_raw = gpio_ra_port_clear_bits_raw, |
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.port_toggle_bits = gpio_ra_port_toggle_bits, |
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#if CONFIG_RENESAS_RA_EXTERNAL_INTERRUPT |
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.pin_interrupt_configure = gpio_ra_pin_interrupt_configure, |
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.manage_callback = gpio_ra_manage_callback, |
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#endif |
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}; |
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#define GPIO_RA_PINS_NAME(n, p, i) CONCAT(DT_STRING_TOKEN_BY_IDX(n, p, i), _pins) |
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#define GPIO_RA_DECL_PINS(n, p, i) \ |
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const uint8_t CONCAT(n, ___pins##i[]) = { \ |
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DT_FOREACH_PROP_ELEM_SEP(n, GPIO_RA_PINS_NAME(n, p, i), DT_PROP_BY_IDX, (,))}; |
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#define GPIO_RA_IRQ_INFO(n, p, i) \ |
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{ \ |
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.port_irq = DEVICE_DT_GET_OR_NULL(DT_PHANDLE_BY_IDX(n, port_irqs, i)), \ |
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.pins = CONCAT(n, ___pins##i), \ |
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.num = ARRAY_SIZE(CONCAT(n, ___pins##i)), \ |
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}, |
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#define DECL_PINS_PARAMETER(node) \ |
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COND_CODE_1(DT_NODE_HAS_PROP(node, port_irq_names), \ |
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(DT_FOREACH_PROP_ELEM(node, port_irq_names, GPIO_RA_DECL_PINS)), ()) |
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#define IRQ_INFO_PARAMETER(node) \ |
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COND_CODE_1(DT_NODE_HAS_PROP(node, port_irq_names), \ |
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(DT_FOREACH_PROP_ELEM(node, port_irq_names, GPIO_RA_IRQ_INFO)), ()) |
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#define GPIO_DEVICE_INIT(node, port_number, suffix, addr) \ |
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DECL_PINS_PARAMETER(node); \ |
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struct gpio_ra_irq_info gpio_ra_irq_info_##suffix[] = {IRQ_INFO_PARAMETER(node)}; \ |
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static const struct gpio_ra_config gpio_ra_config_##suffix = { \ |
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.common = \ |
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{ \ |
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(16U), \ |
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}, \ |
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.port_num = port_number, \ |
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.port = (R_PORT0_Type *)addr, \ |
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.vbatt_pins = DT_PROP_OR(DT_NODELABEL(ioport##suffix), vbatts_pins, {0xFF}), \ |
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.irq_info = gpio_ra_irq_info_##suffix, \ |
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.irq_info_size = DT_PROP_LEN_OR(DT_NODELABEL(ioport##suffix), port_irq_names, 0), \ |
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}; \ |
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static struct gpio_ra_data gpio_ra_data_##suffix; \ |
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DEVICE_DT_DEFINE(node, NULL, NULL, &gpio_ra_data_##suffix, &gpio_ra_config_##suffix, \ |
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PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_drv_api_funcs) |
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#define GPIO_DEVICE_INIT_RA(suffix) \ |
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GPIO_DEVICE_INIT(DT_NODELABEL(ioport##suffix), \ |
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DT_PROP(DT_NODELABEL(ioport##suffix), port), suffix, \ |
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DT_REG_ADDR(DT_NODELABEL(ioport##suffix))) |
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#define GPIO_DEVICE_INIT_RA_IF_OKAY(suffix) \ |
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COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ioport##suffix)), \ |
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(GPIO_DEVICE_INIT_RA(suffix)), \ |
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()) |
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GPIO_DEVICE_INIT_RA_IF_OKAY(0); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(1); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(2); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(3); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(4); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(5); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(6); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(7); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(8); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(9); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(a); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(b); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(c); |
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GPIO_DEVICE_INIT_RA_IF_OKAY(d);
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