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753 lines
22 KiB
753 lines
22 KiB
/* |
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* Copyright (c) 2018, Nordic Semiconductor ASA |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/drivers/counter.h> |
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#include <hal/nrf_rtc.h> |
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#ifdef CONFIG_CLOCK_CONTROL_NRF |
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#include <zephyr/drivers/clock_control.h> |
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#include <zephyr/drivers/clock_control/nrf_clock_control.h> |
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#endif |
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#include <haly/nrfy_rtc.h> |
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#include <zephyr/sys/atomic.h> |
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#ifdef DPPI_PRESENT |
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#include <nrfx_dppi.h> |
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#else |
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#include <nrfx_ppi.h> |
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#endif |
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#define LOG_MODULE_NAME counter_rtc |
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#include <zephyr/logging/log.h> |
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#include <zephyr/irq.h> |
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LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_COUNTER_LOG_LEVEL); |
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#define ERR(...) LOG_INST_ERR( \ |
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((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__) |
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#define WRN(...) LOG_INST_WRN( \ |
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((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__) |
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#define INF(...) LOG_INST_INF( \ |
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((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__) |
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#define DBG(...) LOG_INST_DBG( \ |
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((const struct counter_nrfx_config *)dev->config)->log, __VA_ARGS__) |
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#define DT_DRV_COMPAT nordic_nrf_rtc |
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#define COUNTER_GET_TOP_CH(dev) counter_get_num_of_channels(dev) |
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#define IS_FIXED_TOP(dev) COND_CODE_1(CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT, \ |
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(((const struct counter_nrfx_config *)dev->config)->fixed_top), (true)) |
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#define IS_PPI_WRAP(dev) COND_CODE_1(CONFIG_COUNTER_RTC_WITH_PPI_WRAP, \ |
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(((const struct counter_nrfx_config *)dev->config)->use_ppi), (false)) |
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#define CC_ADJUSTED_OFFSET 16 |
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#define CC_ADJ_MASK(chan) (BIT(chan + CC_ADJUSTED_OFFSET)) |
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#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) |
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#define MAYBE_CONST_CONFIG |
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#else |
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#define MAYBE_CONST_CONFIG const |
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#endif |
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struct counter_nrfx_data { |
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counter_top_callback_t top_cb; |
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void *top_user_data; |
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uint32_t top; |
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uint32_t guard_period; |
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/* Store channel interrupt pending and CC adjusted flags. */ |
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atomic_t ipend_adj; |
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP |
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uint8_t ppi_ch; |
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#endif |
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}; |
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struct counter_nrfx_ch_data { |
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counter_alarm_callback_t callback; |
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void *user_data; |
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}; |
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struct counter_nrfx_config { |
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struct counter_config_info info; |
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struct counter_nrfx_ch_data *ch_data; |
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NRF_RTC_Type *rtc; |
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP |
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bool use_ppi; |
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#endif |
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#if CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT |
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bool fixed_top; |
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#endif |
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LOG_INSTANCE_PTR_DECLARE(log); |
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}; |
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static int start(const struct device *dev) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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nrfy_rtc_task_trigger(config->rtc, NRF_RTC_TASK_START); |
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return 0; |
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} |
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static int stop(const struct device *dev) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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nrfy_rtc_task_trigger(config->rtc, NRF_RTC_TASK_STOP); |
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return 0; |
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} |
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static uint32_t read(const struct device *dev) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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return nrfy_rtc_counter_get(config->rtc); |
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} |
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static int get_value(const struct device *dev, uint32_t *ticks) |
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{ |
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*ticks = read(dev); |
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return 0; |
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} |
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/* Function calculates distance between to values assuming that one first |
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* argument is in front and that values wrap. |
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*/ |
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static uint32_t ticks_sub(const struct device *dev, uint32_t val, |
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uint32_t old, uint32_t top) |
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{ |
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if (IS_FIXED_TOP(dev)) { |
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return (val - old) & NRF_RTC_COUNTER_MAX; |
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} else if (likely(IS_BIT_MASK(top))) { |
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return (val - old) & top; |
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} |
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/* if top is not 2^n-1 */ |
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return (val >= old) ? (val - old) : val + top + 1 - old; |
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} |
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static uint32_t skip_zero_on_custom_top(uint32_t val, uint32_t top) |
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{ |
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/* From Product Specification: If a CC register value is 0 when |
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* a CLEAR task is set, this will not trigger a COMPARE event. |
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*/ |
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if (unlikely(val == 0) && (top != NRF_RTC_COUNTER_MAX)) { |
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val++; |
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} |
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return val; |
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} |
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static uint32_t ticks_add(const struct device *dev, uint32_t val1, |
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uint32_t val2, uint32_t top) |
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{ |
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uint32_t sum = val1 + val2; |
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if (IS_FIXED_TOP(dev)) { |
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ARG_UNUSED(top); |
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return sum & NRF_RTC_COUNTER_MAX; |
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} |
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if (likely(IS_BIT_MASK(top))) { |
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sum = sum & top; |
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} else { |
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sum = sum > top ? sum - (top + 1) : sum; |
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} |
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return skip_zero_on_custom_top(sum, top); |
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} |
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static void set_cc_int_pending(const struct device *dev, uint8_t chan) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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struct counter_nrfx_data *data = dev->data; |
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atomic_or(&data->ipend_adj, BIT(chan)); |
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NRFY_IRQ_PENDING_SET(NRFX_IRQ_NUMBER_GET(config->rtc)); |
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} |
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/** @brief Handle case when CC value equals COUNTER+1. |
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* |
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* RTC will not generate event if CC value equals COUNTER+1. If such CC is |
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* about to be set then special algorithm is applied. Since counter must not |
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* expire before expected value, CC is set to COUNTER+2. If COUNTER progressed |
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* during that time it means that target value is reached and interrupt is |
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* manually triggered. If not then interrupt is enabled since it is expected |
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* that CC value will generate event. |
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* |
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* Additionally, an information about CC adjustment is stored. This information |
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* is used in the callback to return original CC value which was requested by |
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* the user. |
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*/ |
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static void handle_next_tick_case(const struct device *dev, uint8_t chan, |
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uint32_t now, uint32_t val) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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struct counter_nrfx_data *data = dev->data; |
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val = ticks_add(dev, val, 1, data->top); |
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nrfy_rtc_cc_set(config->rtc, chan, val); |
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atomic_or(&data->ipend_adj, CC_ADJ_MASK(chan)); |
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if (nrfy_rtc_counter_get(config->rtc) != now) { |
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set_cc_int_pending(dev, chan); |
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} else { |
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nrfy_rtc_int_enable(config->rtc, NRF_RTC_CHANNEL_INT_MASK(chan)); |
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} |
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} |
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/* |
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* @brief Set COMPARE value with optional too late setting detection. |
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* |
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* Setting CC algorithm takes into account: |
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* - Current COMPARE value written to the register may be close to the current |
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* COUNTER value thus COMPARE event may be generated at any moment |
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* - Next COMPARE value may be soon in the future. Taking into account potential |
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* preemption COMPARE value may be set too late. |
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* - RTC registers are clocked with LF clock (32kHz) and sampled between two |
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* LF ticks. |
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* - Setting COMPARE register to COUNTER+1 does not generate COMPARE event if |
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* done half tick before tick boundary. |
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* |
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* Algorithm assumes that: |
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* - COMPARE interrupt is disabled |
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* - absolute value is taking into account guard period. It means that |
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* it won't be further in future than <top> - <guard_period> from now. |
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* |
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* @param dev Device. |
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* @param chan COMPARE channel. |
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* @param val Value (absolute or relative). |
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* @param flags Alarm flags. |
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* |
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* @retval 0 if COMPARE value was set on time and COMPARE interrupt is expected. |
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* @retval -ETIME if absolute alarm was set too late and error reporting is |
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* enabled. |
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* |
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*/ |
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static int set_cc(const struct device *dev, uint8_t chan, uint32_t val, |
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uint32_t flags) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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struct counter_nrfx_data *data = dev->data; |
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__ASSERT_NO_MSG(data->guard_period < data->top); |
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NRF_RTC_Type *rtc = config->rtc; |
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nrf_rtc_event_t evt; |
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uint32_t prev_val; |
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uint32_t top; |
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uint32_t now; |
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uint32_t diff; |
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uint32_t int_mask = NRF_RTC_CHANNEL_INT_MASK(chan); |
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int err = 0; |
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uint32_t max_rel_val; |
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bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE; |
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bool irq_on_late; |
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__ASSERT(nrf_rtc_int_enable_check(rtc, int_mask) == 0, |
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"Expected that CC interrupt is disabled."); |
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evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan); |
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top = data->top; |
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now = nrfy_rtc_counter_get(rtc); |
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/* First take care of a risk of an event coming from CC being set to |
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* next tick. Reconfigure CC to future (now tick is the furthest |
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* future). If CC was set to next tick we need to wait for up to 15us |
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* (half of 32k tick) and clean potential event. After that time there |
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* is no risk of unwanted event. |
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*/ |
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prev_val = nrfy_rtc_cc_get(rtc, chan); |
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nrfy_rtc_event_clear(rtc, evt); |
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nrfy_rtc_cc_set(rtc, chan, now); |
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nrfy_rtc_event_enable(rtc, int_mask); |
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if (ticks_sub(dev, prev_val, now, top) == 1) { |
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NRFX_DELAY_US(15); |
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nrfy_rtc_event_clear(rtc, evt); |
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} |
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now = nrfy_rtc_counter_get(rtc); |
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if (absolute) { |
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val = skip_zero_on_custom_top(val, top); |
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irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE; |
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max_rel_val = top - data->guard_period; |
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} else { |
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/* If relative value is smaller than half of the counter range |
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* it is assumed that there is a risk of setting value too late |
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* and late detection algorithm must be applied. When late |
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* setting is detected, interrupt shall be triggered for |
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* immediate expiration of the timer. Detection is performed |
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* by limiting relative distance between CC and counter. |
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* |
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* Note that half of counter range is an arbitrary value. |
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*/ |
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irq_on_late = val < (top / 2); |
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/* limit max to detect short relative being set too late. */ |
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max_rel_val = irq_on_late ? top / 2 : top; |
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val = ticks_add(dev, now, val, top); |
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} |
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diff = ticks_sub(dev, val, now, top); |
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if (diff == 1) { |
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/* CC cannot be set to COUNTER+1 because that will not |
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* generate an event. In that case, special handling is |
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* performed (attempt to set CC to COUNTER+2). |
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*/ |
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handle_next_tick_case(dev, chan, now, val); |
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} else { |
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nrfy_rtc_cc_set(rtc, chan, val); |
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now = nrfy_rtc_counter_get(rtc); |
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/* decrement value to detect also case when val == read(dev). |
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* Otherwise, condition would need to include comparing diff |
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* against 0. |
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*/ |
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diff = ticks_sub(dev, val - 1, now, top); |
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if (diff > max_rel_val) { |
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if (absolute) { |
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err = -ETIME; |
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} |
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/* Interrupt is triggered always for relative alarm and |
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* for absolute depending on the flag. |
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*/ |
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if (irq_on_late) { |
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set_cc_int_pending(dev, chan); |
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} else { |
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config->ch_data[chan].callback = NULL; |
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} |
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} else if (diff == 0) { |
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/* It is possible that setting CC was interrupted and |
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* CC might be set to COUNTER+1 value which will not |
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* generate an event. In that case, special handling |
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* is performed (attempt to set CC to COUNTER+2). |
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*/ |
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handle_next_tick_case(dev, chan, now, val); |
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} else { |
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nrfy_rtc_int_enable(rtc, int_mask); |
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} |
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} |
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return err; |
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} |
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static int set_channel_alarm(const struct device *dev, uint8_t chan, |
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const struct counter_alarm_cfg *alarm_cfg) |
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{ |
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const struct counter_nrfx_config *nrfx_config = dev->config; |
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struct counter_nrfx_data *data = dev->data; |
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struct counter_nrfx_ch_data *chdata = &nrfx_config->ch_data[chan]; |
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if (alarm_cfg->ticks > data->top) { |
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return -EINVAL; |
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} |
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if (chdata->callback) { |
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return -EBUSY; |
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} |
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chdata->callback = alarm_cfg->callback; |
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chdata->user_data = alarm_cfg->user_data; |
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atomic_and(&data->ipend_adj, ~CC_ADJ_MASK(chan)); |
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return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags); |
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} |
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static void disable(const struct device *dev, uint8_t chan) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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NRF_RTC_Type *rtc = config->rtc; |
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nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan); |
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nrfy_rtc_event_int_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan)); |
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nrfy_rtc_event_clear(rtc, evt); |
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config->ch_data[chan].callback = NULL; |
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} |
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static int cancel_alarm(const struct device *dev, uint8_t chan_id) |
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{ |
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disable(dev, chan_id); |
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return 0; |
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} |
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static int ppi_setup(const struct device *dev, uint8_t chan) |
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{ |
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP |
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const struct counter_nrfx_config *nrfx_config = dev->config; |
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struct counter_nrfx_data *data = dev->data; |
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NRF_RTC_Type *rtc = nrfx_config->rtc; |
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nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan); |
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nrfx_err_t result; |
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if (!nrfx_config->use_ppi) { |
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return 0; |
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} |
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nrfy_rtc_event_enable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan)); |
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#ifdef DPPI_PRESENT |
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nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0); |
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result = nrfx_dppi_channel_alloc(&dppi, &data->ppi_ch); |
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if (result != NRFX_SUCCESS) { |
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ERR("Failed to allocate PPI channel."); |
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return -ENODEV; |
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} |
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nrfy_rtc_subscribe_set(rtc, NRF_RTC_TASK_CLEAR, data->ppi_ch); |
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nrfy_rtc_publish_set(rtc, evt, data->ppi_ch); |
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(void)nrfx_dppi_channel_enable(&dppi, data->ppi_ch); |
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#else /* DPPI_PRESENT */ |
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uint32_t evt_addr; |
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uint32_t task_addr; |
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evt_addr = nrfy_rtc_event_address_get(rtc, evt); |
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task_addr = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR); |
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result = nrfx_ppi_channel_alloc(&data->ppi_ch); |
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if (result != NRFX_SUCCESS) { |
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ERR("Failed to allocate PPI channel."); |
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return -ENODEV; |
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} |
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(void)nrfx_ppi_channel_assign(data->ppi_ch, evt_addr, task_addr); |
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(void)nrfx_ppi_channel_enable(data->ppi_ch); |
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#endif |
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#endif /* CONFIG_COUNTER_RTC_WITH_PPI_WRAP */ |
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return 0; |
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} |
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static void ppi_free(const struct device *dev, uint8_t chan) |
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{ |
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#if CONFIG_COUNTER_RTC_WITH_PPI_WRAP |
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const struct counter_nrfx_config *nrfx_config = dev->config; |
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struct counter_nrfx_data *data = dev->data; |
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uint8_t ppi_ch = data->ppi_ch; |
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NRF_RTC_Type *rtc = nrfx_config->rtc; |
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if (!nrfx_config->use_ppi) { |
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return; |
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} |
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nrfy_rtc_event_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan)); |
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#ifdef DPPI_PRESENT |
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nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan); |
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nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0); |
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(void)nrfx_dppi_channel_disable(&dppi, ppi_ch); |
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nrfy_rtc_subscribe_clear(rtc, NRF_RTC_TASK_CLEAR); |
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nrfy_rtc_publish_clear(rtc, evt); |
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(void)nrfx_dppi_channel_free(&dppi, ppi_ch); |
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#else /* DPPI_PRESENT */ |
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(void)nrfx_ppi_channel_disable(ppi_ch); |
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(void)nrfx_ppi_channel_free(ppi_ch); |
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#endif |
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#endif |
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} |
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/* Return true if counter must be cleared by the CPU. It is cleared |
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* automatically in case of max top value or PPI usage. |
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*/ |
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static bool sw_wrap_required(const struct device *dev) |
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{ |
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struct counter_nrfx_data *data = dev->data; |
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return (data->top != NRF_RTC_COUNTER_MAX) && !IS_PPI_WRAP(dev); |
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} |
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static int set_fixed_top_value(const struct device *dev, |
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const struct counter_top_cfg *cfg) |
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{ |
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const struct counter_nrfx_config *config = dev->config; |
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struct counter_nrfx_data *data = dev->data; |
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NRF_RTC_Type *rtc = config->rtc; |
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if (cfg->ticks != NRF_RTC_COUNTER_MAX) { |
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return -EINVAL; |
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} |
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nrfy_rtc_int_disable(rtc, NRF_RTC_INT_OVERFLOW_MASK); |
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data->top_cb = cfg->callback; |
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data->top_user_data = cfg->user_data; |
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if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) { |
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nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR); |
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} |
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if (cfg->callback) { |
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nrfy_rtc_int_enable(rtc, NRF_RTC_INT_OVERFLOW_MASK); |
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} |
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return 0; |
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} |
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static int set_top_value(const struct device *dev, |
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const struct counter_top_cfg *cfg) |
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{ |
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const struct counter_nrfx_config *nrfx_config = dev->config; |
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NRF_RTC_Type *rtc = nrfx_config->rtc; |
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struct counter_nrfx_data *dev_data = dev->data; |
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uint32_t top_ch = COUNTER_GET_TOP_CH(dev); |
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int err = 0; |
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|
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if (IS_FIXED_TOP(dev)) { |
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return set_fixed_top_value(dev, cfg); |
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} |
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for (int i = 0; i < counter_get_num_of_channels(dev); i++) { |
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/* Overflow can be changed only when all alarms are |
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* disables. |
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*/ |
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if (nrfx_config->ch_data[i].callback) { |
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return -EBUSY; |
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} |
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} |
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nrfy_rtc_int_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(top_ch)); |
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if (IS_PPI_WRAP(dev)) { |
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if ((dev_data->top == NRF_RTC_COUNTER_MAX) && |
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cfg->ticks != NRF_RTC_COUNTER_MAX) { |
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err = ppi_setup(dev, top_ch); |
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} else if (((dev_data->top != NRF_RTC_COUNTER_MAX) && |
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cfg->ticks == NRF_RTC_COUNTER_MAX)) { |
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ppi_free(dev, top_ch); |
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} |
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} |
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dev_data->top_cb = cfg->callback; |
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dev_data->top_user_data = cfg->user_data; |
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dev_data->top = cfg->ticks; |
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nrfy_rtc_cc_set(rtc, top_ch, cfg->ticks); |
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|
|
if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) { |
|
nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR); |
|
} else if (read(dev) >= cfg->ticks) { |
|
err = -ETIME; |
|
if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) { |
|
nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR); |
|
} |
|
} |
|
|
|
if (cfg->callback || sw_wrap_required(dev)) { |
|
nrfy_rtc_int_enable(rtc, NRF_RTC_CHANNEL_INT_MASK(top_ch)); |
|
} |
|
|
|
return err; |
|
} |
|
|
|
static uint32_t get_pending_int(const struct device *dev) |
|
{ |
|
return 0; |
|
} |
|
|
|
static int init_rtc(const struct device *dev, uint32_t prescaler) |
|
{ |
|
MAYBE_CONST_CONFIG struct counter_nrfx_config *nrfx_config = |
|
(MAYBE_CONST_CONFIG struct counter_nrfx_config *) dev->config; |
|
struct counter_nrfx_data *data = dev->data; |
|
struct counter_top_cfg top_cfg = { |
|
.ticks = NRF_RTC_COUNTER_MAX |
|
}; |
|
|
|
#if defined(CONFIG_SOC_SERIES_BSIM_NRFXX) |
|
/* For simulated devices we need to convert the hardcoded DT address from the real |
|
* peripheral into the correct one for simulation |
|
*/ |
|
nrfx_config->rtc = nhw_convert_periph_base_addr(nrfx_config->rtc); |
|
#endif |
|
|
|
NRF_RTC_Type *rtc = nrfx_config->rtc; |
|
int err; |
|
|
|
#ifdef CONFIG_CLOCK_CONTROL_NRF |
|
z_nrf_clock_control_lf_on(CLOCK_CONTROL_NRF_LF_START_NOWAIT); |
|
#endif |
|
|
|
nrfy_rtc_prescaler_set(rtc, prescaler); |
|
|
|
NRFY_IRQ_ENABLE(NRFX_IRQ_NUMBER_GET(rtc)); |
|
|
|
data->top = NRF_RTC_COUNTER_MAX; |
|
err = set_top_value(dev, &top_cfg); |
|
DBG("Initialized"); |
|
|
|
return err; |
|
} |
|
|
|
static uint32_t get_top_value(const struct device *dev) |
|
{ |
|
struct counter_nrfx_data *data = dev->data; |
|
|
|
return data->top; |
|
} |
|
|
|
static uint32_t get_guard_period(const struct device *dev, uint32_t flags) |
|
{ |
|
struct counter_nrfx_data *data = dev->data; |
|
|
|
return data->guard_period; |
|
} |
|
|
|
static int set_guard_period(const struct device *dev, uint32_t guard, |
|
uint32_t flags) |
|
{ |
|
struct counter_nrfx_data *data = dev->data; |
|
|
|
data->guard_period = guard; |
|
return 0; |
|
} |
|
|
|
static void top_irq_handle(const struct device *dev) |
|
{ |
|
const struct counter_nrfx_config *config = dev->config; |
|
struct counter_nrfx_data *data = dev->data; |
|
|
|
NRF_RTC_Type *rtc = config->rtc; |
|
counter_top_callback_t cb = data->top_cb; |
|
nrf_rtc_event_t top_evt; |
|
|
|
top_evt = IS_FIXED_TOP(dev) ? |
|
NRF_RTC_EVENT_OVERFLOW : |
|
NRF_RTC_CHANNEL_EVENT_ADDR(counter_get_num_of_channels(dev)); |
|
|
|
uint32_t event_mask = nrfy_rtc_events_process(rtc, NRFY_EVENT_TO_INT_BITMASK(top_evt)); |
|
|
|
if (event_mask & NRFY_EVENT_TO_INT_BITMASK(top_evt)) { |
|
/* Perform manual clear if custom top value is used and PPI |
|
* clearing is not used. |
|
*/ |
|
if (!IS_FIXED_TOP(dev) && !IS_PPI_WRAP(dev)) { |
|
nrfy_rtc_task_trigger(rtc, NRF_RTC_TASK_CLEAR); |
|
} |
|
|
|
if (cb) { |
|
cb(dev, data->top_user_data); |
|
} |
|
} |
|
} |
|
|
|
static void alarm_irq_handle(const struct device *dev, uint32_t chan) |
|
{ |
|
const struct counter_nrfx_config *config = dev->config; |
|
struct counter_nrfx_data *data = dev->data; |
|
|
|
NRF_RTC_Type *rtc = config->rtc; |
|
nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan); |
|
uint32_t int_mask = NRF_RTC_CHANNEL_INT_MASK(chan); |
|
|
|
bool hw_irq_pending = nrfy_rtc_events_process(rtc, NRFY_EVENT_TO_INT_BITMASK(evt)) & |
|
nrfy_rtc_int_enable_check(rtc, NRFY_EVENT_TO_INT_BITMASK(evt)); |
|
bool sw_irq_pending = data->ipend_adj & BIT(chan); |
|
|
|
if (hw_irq_pending || sw_irq_pending) { |
|
struct counter_nrfx_ch_data *chdata; |
|
counter_alarm_callback_t cb; |
|
|
|
atomic_and(&data->ipend_adj, ~BIT(chan)); |
|
nrfy_rtc_int_disable(rtc, int_mask); |
|
|
|
chdata = &config->ch_data[chan]; |
|
cb = chdata->callback; |
|
chdata->callback = NULL; |
|
|
|
if (cb) { |
|
uint32_t cc = nrfy_rtc_cc_get(rtc, chan); |
|
|
|
if (data->ipend_adj & CC_ADJ_MASK(chan)) { |
|
cc = ticks_sub(dev, cc, 1, data->top); |
|
} |
|
|
|
cb(dev, chan, cc, chdata->user_data); |
|
} |
|
} |
|
} |
|
|
|
static void irq_handler(const void *arg) |
|
{ |
|
const struct device *dev = arg; |
|
|
|
top_irq_handle(dev); |
|
|
|
for (uint32_t i = 0; i < counter_get_num_of_channels(dev); i++) { |
|
alarm_irq_handle(dev, i); |
|
} |
|
} |
|
|
|
static DEVICE_API(counter, counter_nrfx_driver_api) = { |
|
.start = start, |
|
.stop = stop, |
|
.get_value = get_value, |
|
.set_alarm = set_channel_alarm, |
|
.cancel_alarm = cancel_alarm, |
|
.set_top_value = set_top_value, |
|
.get_pending_int = get_pending_int, |
|
.get_top_value = get_top_value, |
|
.get_guard_period = get_guard_period, |
|
.set_guard_period = set_guard_period, |
|
}; |
|
|
|
/* |
|
* Devicetree access is done with node labels due to HAL API |
|
* requirements. In particular, RTCx_CC_NUM values from HALs |
|
* are indexed by peripheral number, so DT_INST APIs won't work. |
|
*/ |
|
|
|
#define RTC_IRQ_CONNECT(idx) \ |
|
COND_CODE_1(DT_INST_PROP(idx, zli), \ |
|
(IRQ_DIRECT_CONNECT(DT_INST_IRQN(idx), \ |
|
DT_INST_IRQ(idx, priority), \ |
|
counter_rtc##idx##_isr_wrapper, \ |
|
IRQ_ZERO_LATENCY)), \ |
|
(IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), \ |
|
irq_handler, DEVICE_DT_INST_GET(idx), 0)) \ |
|
) |
|
|
|
#define COUNTER_NRF_RTC_DEVICE(idx) \ |
|
BUILD_ASSERT((DT_INST_PROP(idx, prescaler) - 1) <= \ |
|
RTC_PRESCALER_PRESCALER_Msk, \ |
|
"RTC prescaler out of range"); \ |
|
COND_CODE_1(DT_INST_PROP(idx, zli), ( \ |
|
ISR_DIRECT_DECLARE(counter_rtc##idx##_isr_wrapper) \ |
|
{ \ |
|
irq_handler(DEVICE_DT_INST_GET(idx)); \ |
|
/* No rescheduling, it shall not access zephyr primitives. */ \ |
|
return 0; \ |
|
}), ()) \ |
|
static int counter_##idx##_init(const struct device *dev) \ |
|
{ \ |
|
RTC_IRQ_CONNECT(idx); \ |
|
return init_rtc(dev, DT_INST_PROP(idx, prescaler) - 1); \ |
|
} \ |
|
static struct counter_nrfx_data counter_##idx##_data; \ |
|
static struct counter_nrfx_ch_data \ |
|
counter##idx##_ch_data[DT_INST_PROP(idx, cc_num)]; \ |
|
LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \ |
|
static MAYBE_CONST_CONFIG \ |
|
struct counter_nrfx_config nrfx_counter_##idx##_config = { \ |
|
.info = { \ |
|
.max_top_value = NRF_RTC_COUNTER_MAX, \ |
|
.freq = DT_INST_PROP(idx, clock_frequency) / \ |
|
DT_INST_PROP(idx, prescaler), \ |
|
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \ |
|
.channels = DT_INST_PROP(idx, fixed_top) \ |
|
? DT_INST_PROP(idx, cc_num) \ |
|
: DT_INST_PROP(idx, cc_num) - 1 \ |
|
}, \ |
|
.ch_data = counter##idx##_ch_data, \ |
|
.rtc = (NRF_RTC_Type *)DT_INST_REG_ADDR(idx), \ |
|
IF_ENABLED(CONFIG_COUNTER_RTC_WITH_PPI_WRAP, \ |
|
(.use_ppi = DT_INST_PROP(idx, ppi_wrap),)) \ |
|
IF_ENABLED(CONFIG_COUNTER_RTC_CUSTOM_TOP_SUPPORT, \ |
|
(.fixed_top = DT_INST_PROP(idx, fixed_top),)) \ |
|
LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx) \ |
|
}; \ |
|
DEVICE_DT_INST_DEFINE(idx, \ |
|
counter_##idx##_init, \ |
|
NULL, \ |
|
&counter_##idx##_data, \ |
|
&nrfx_counter_##idx##_config.info, \ |
|
PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \ |
|
&counter_nrfx_driver_api); |
|
|
|
DT_INST_FOREACH_STATUS_OKAY(COUNTER_NRF_RTC_DEVICE)
|
|
|